Cypress CY62137FV30 Truth Table

CY62137FV30 MoBL®

Document Number: 001-07141 Rev. *F Page 9 of 12

Truth Table

CE WE OE BHE BLE Inputs or Outputs Mode Power

HXXXXHigh Z Deselect or Power Down Standby (I

SB)

X X X H H High Z Deselect or Power Down Standby (ISB)

L H L L L Data Out (IO0–IO15)Read Active (I

CC)

LHLHLData Out (IO

0–IO7);

IO8–IO15 in High Z Read Active (ICC)

L H L L H Data Out (IO8–IO15);

IO0–IO7 in High Z Read Active (ICC)

L H H L L High Z Output Disabled Active (ICC)

L H H H L High Z Output Disabled Active (ICC)

L H H L H High Z Output Disabled Active (ICC)

L L X L L Data In (IO0–IO15) Write Active (ICC)

L L X H L Data In (IO0–IO7);

IO8–IO15 in High Z Write Active (ICC)

L L X L H Data In (IO8–IO15);

IO0–IO7 in High Z Write Active (ICC)

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Contents

Main CY62137FV30 MoBL 2-Mbit (128K x 16) Static RAM Features Functional Description Logic Block Diagram CY62137FV30 MoBL Document Number: 001-07141 Rev. *F Page 2 of 12 Product Portfolio Product Range VCC Range (V) Speed (ns) Pin Configuration CY62137FV30 MoBL Maximum Ratings Operating Range Electrical Characteristics Capacitance Thermal Resistance AC Test Loads and Waveforms Data Retention Characteristics Data Retention Waveform Switching Characteristics CY62137FV30 MoBL Document Number: 001-07141 Rev. *F Page 6 of 12 PREVIOUS DATA VALID DATA VALID Switching Waveforms Figure 5. Read Cycle 1: Address Transition Controlled [17, 18] CY62137FV30 MoBL Document Number: 001-07141 Rev. *F Page 7 of 12 Figure 7. Write Cycle 1: WE Controlled [16, 20, 21] t Figure 8. Write Cycle 2: CE Controlled [16, 20, 21] Document Number: 001-07141 Rev. *F Page 8 of 12 Figure 9. Write Cycle 3: WE Controlled, OE LOW [21] Figure 10. Write Cycle 4: BHE/BLE Controlled, OE LOW [21] Truth Table Document Number: 001-07141 Rev. *F Page 10 of 12 Ordering Information Diagram Package Type Operating Speed (ns) Ordering Code Package Package Diagram Figure 11. 48-Ball VFBGA (6 x 8 x 1 mm) 51-85150-*D Page Document History Page