Cypress CY62137FV30 CY62137FV30 MoBL

CY62137FV30 MoBL®

Document Number: 001-07141 Rev. *F Page 6 of 12

Switching Waveforms

Figure 5. Read Cycle 1: Address Transition Controlled [17, 18]

Figure 6. Read Cycle 2: OE Controlled [18, 19]

PREVIOUS DATA VALID DATA VALID

tRC

tAA

tOHA

ADDRESS

DATA OUT

50%

DATA VALID

ACE

LZBE

LZCE

HIGH IMPEDANCE

HZOE

HZCE

HZBE

LZOE

DBE

DOE

IMPEDANCE

HIGH

DATA OUT

SUPPLY

CURRENT

BHE/BLE

ADDRESS

Notes

17.The device is continuously selected. OE, CE = VIL, BHE and/or BLE = VIL.

18.WE is HIGH for read cycle.

19.Address valid before or similar to CE and BHE, BLE transition LOW.

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Contents

Main CY62137FV30 MoBL 2-Mbit (128K x 16) Static RAM Features Functional Description Logic Block Diagram CY62137FV30 MoBL Document Number: 001-07141 Rev. *F Page 2 of 12 Product Portfolio Product Range VCC Range (V) Speed (ns) Pin Configuration CY62137FV30 MoBL Maximum Ratings Operating Range Electrical Characteristics Capacitance Thermal Resistance AC Test Loads and Waveforms Data Retention Characteristics Data Retention Waveform Switching Characteristics CY62137FV30 MoBL Document Number: 001-07141 Rev. *F Page 6 of 12 PREVIOUS DATA VALID DATA VALID Switching Waveforms Figure 5. Read Cycle 1: Address Transition Controlled [17, 18] CY62137FV30 MoBL Document Number: 001-07141 Rev. *F Page 7 of 12 Figure 7. Write Cycle 1: WE Controlled [16, 20, 21] t Figure 8. Write Cycle 2: CE Controlled [16, 20, 21] Document Number: 001-07141 Rev. *F Page 8 of 12 Figure 9. Write Cycle 3: WE Controlled, OE LOW [21] Figure 10. Write Cycle 4: BHE/BLE Controlled, OE LOW [21] Truth Table Document Number: 001-07141 Rev. *F Page 10 of 12 Ordering Information Diagram Package Type Operating Speed (ns) Ordering Code Package Package Diagram Figure 11. 48-Ball VFBGA (6 x 8 x 1 mm) 51-85150-*D Page Document History Page