Cypress CY62146DV30 Switching Waveforms

CY62146DV30

Document #: 38-05339 Rev. *A Page 7 of 11

Write Cycle No. 1 (WE Controlled)[15, 19, 20]

Write Cycle No. 2 (CE Controlled)[15, 19, 20]

Notes:

19.Data I/O is high impedance if OE = VIH.

20.If CE goes HIGH simultaneously with WE = VIH, the output remains in a high-impedance state.

21.During this period, the I/Os are in output state and input signals should not be applied.

Switching Waveforms (continued)

tHD

tSD

tPWE

tSA

tHA

tAW

tWC

DATA I/O

ADDRESS

tHZOE

DATAIN

NOTE 21

BHE/BLE tBW

tSCE

tHD

tSD

tPWE

tHA

tAW

tSCE

tWC

tHZOE

DATAIN

ADDRESS

DATA I/O

NOTE21

BHE/BLE tBW

tSA

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Contents

Main 4-Mbit (256K x 16) Static RAM CY62146DV30 Features Functional Description Logic Block Diagram CY62146DV30 Pin Configuration Product VFBGA (Top View) 44 TSOP II (Top View) Product Portfolio CY62146DV30 Maximum Ratings Operating Range Electrical Characteristics CY62146DV30 Capacitance Thermal Resistance AC Test Loads and Waveforms Data Retention Characteristics Switching Characteristics CY62146DV30 Switching Waveforms Read Cycle 1 (Address Transition Controlled) Read Cycle No. 2 (OE Controlled)[17, 18] ADDRESS DATA OUT PREVIOUS DATA VALID DATA VALID Switching Waveforms t Document #: 38-05339 Rev. *A Page 8 of 11 Write Cycle No. 3 (WE Controlled, OE LOW)[20] Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[20] Truth Table Ordering Information Package Diagram Document History Page