Cypress CY62146DV30 manual Features, Functional Description1, Logic Block Diagram

CY62146DV30

4-Mbit (256K x 16) Static RAM

Features

•Very high speed: 45 ns

•Wide voltage range: 2.20V–3.60V

•Pin-compatible with CY62146CV30

•Ultra-low active power

—Typical active current: 1.5 mA @ f = 1 MHz

—Typical active current: 8 mA @ f = fmax

•Ultra low standby power

•Easy memory expansion with CE, and OE features

•Automatic power-down when deselected

•CMOS for optimum speed/power

•Packages offered 48-ball BGA and 44-pin TSOPII

•Also available in Lead-free packages

Functional Description[1]

The CY62146DV30 is a high-performance CMOS static RAM organized as 256K words by 16 bits. This device features ad- vanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life™ (MoBL) in portable applications such as cellular telephones. The device also has

an automatic power-down feature that significantly reduces power consumption. The device can also be put into standby mode reducing power consumption by more than 99% when deselected (CE HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE HIGH), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation (CE LOW and WE LOW).

Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A17).

Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes.

The CY62146DV30 is available in a 48-ball VFBGA, 44-pin TSOPII packages.

Logic Block Diagram

A10

A9

A8	DECODER
A4
A7
A6
A5
A3	ROW
A2
A1
A0

DATA IN DRIVERS

256K x 16 RAM Array

SENSE AMPS

I/O0–I/O7

I/O8–I/O15

COLUMN DECODER
							BHE
							WE
11	12	13	14	15	16	17	CE
A	A	A	A A A			A	OE
							BLE

Note:

1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.

Cypress Semiconductor Corporation	•	3901 North First Street	•	San Jose, CA 95134	•	408-943-2600
Document #: 38-05339 Rev. *A				Revised February 2, 2005

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