Cypress CY62146E MoBL Switching Waveforms

CY62146E MoBL®

Document Number: 001-07970 Rev. *D Page 7 of 11

Figure 6. Write Cycle No 1: WE Controlled [13, 17, 18]

Figure 7. Write Cycle 2: CE Controlled [13, 17, 18]

Switching Waveforms (continued)

tHD

tSD

tPWE

tSA

tHA

tAW

tWC

tHZOE

DATAIN

NOTE 19

tBW

tSCE

DATA IO

ADDRESS

BHE/BLE

tHD

tSD

tPWE

tHA

tAW

tSCE

tWC

tHZOE

DATAIN

tBW

tSA

ADDRESS

DATA IO

BHE/BLE

NOTE 19

Notes

17.Data IO is high impedance if OE = VIH.

18.If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.

19.During this period, the IOs are in output state. Do not apply input signals.

[+] Feedback [+] Feedback

Contents

Main CY62146E MoBL 4-Mbit (256K x 16) Static RAM Features Functional Description Logic Block Diagram CY62146E MoBL Pin Configuration Figure 1. 44-Pin TSOP II (Top View) Product Portfolio Product Range VCC Range (V) Speed (ns) Maximum Ratings Operating Range Electrical Characteristics Capacitance Thermal Resistance CY62146E MoBL Data Retention Characteristics Switching Characteristics CY62146E MoBL Switching Waveforms Figure 4. Read Cycle No.1: Address Transition Controlled. [14, 15] Figure 5. Read Cycle No. 2: OE Controlled [15, 16] Document Number: 001-07970 Rev. *D Page 7 of 11 Switching Waveforms Figure 8. Write Cycle 3: WE controlled, OE LOW [18] Figure 9. Write Cycle 4: BHE/BLE Controlled, OE LOW [18] Ordering Information Page Document History Page