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Cypress CY62146ESL Data Retention Characteristics , Data Retention Waveform

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CY62146ESL MoBL®

Document #: 001-43142 Rev. ** Page 5 of 12

Data Retention Characteristics

Over the Operating Range

Parameter Description Conditions Min Typ[3] Max Unit

VDR VCC for Data Retention 1.5 V

ICCDR Data Retention Current CE > VCC – 0.2V,

VIN > VCC – 0.2V or VIN < 0.2V VCC = 1.5V 1 7 μA

tCDR [7] Chip Deselect to Data

Retention Time 0ns

tR [8] Operation Recovery Time tRC ns

Data Retention Waveform

Notes

7. Tested initially and after any design or process changes that may affect these parameters.

8. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 μs or stable at VCC(min) > 100 μs.

VCC(min)

tCDR

VDR>1.5V

DATA RETENTION MODE

VCC

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Contents

Main CY62146ESL MoBL 4-Mbit (256K x 16) Static RAM Features Functional Description Logic Block Diagram CY62146ESL MoBL Document #: 001-43142 Rev. ** Page 2 of 12 Pin Configuration Figure 1. 44-Pin TSOP II (Top View) Product Portfolio Maximum Ratings Operating Range Electrical Characteristics CY62146ESL MoBL Capacitance Thermal Resistance AC Test Loads and Waveforms Data Retention Characteristics Data Retention Waveform CY62146ESL MoBL Switching Characteristics Switching Waveforms Figure 2. Read Cycle No.1: Address Transition Controlled. [13, 14] Figure 3. Read Cycle No. 2: OE Controlled [14, 15] Figure 4. Write Cycle No 1: WE Controlled [12, 16, 17] Figure 5. Write Cycle 2: CE Controlled [12, 16, 17] Switching Waveforms Figure 6. Write Cycle 3: WE controlled, OE LOW [17] Figure 7. Write Cycle 4: BHE/BLE Controlled, OE LOW [17] Switching Waveforms Truth Table Ordering Information Page Document History Page