CY62146ESL MoBL®
Document #: 001-43142 Rev. ** Page 6 of 12
Switching Characteristics
Over the Operating Range [9]
Parameter Description 45 ns Unit
Min Max
Read Cycle
tRC Read Cycle Time 45 ns
tAA Address to Data Valid 45 ns
tOHA Data Hold from Address Change 10 ns
tACE CE LOW to Data Valid 45 ns
tDOE OE LOW to Data Valid 22 ns
tLZOE OE LOW to LOW-Z[10] 5ns
tHZOE OE HIGH to High-Z[10, 11] 18 ns
tLZCE CE LOW to Low-Z[10] 10 ns
tHZCE CE HIGH to High-Z[10, 11] 18 ns
tPU CE LOW to Power Up 0 ns
tPD CE HIGH to Power Down 45 ns
tDBE BLE/BHE LOW to Data Valid 22 ns
tLZBE BLE/BHE LOW to Low-Z[10] 5ns
tHZBE BLE/BHE HIGH to HIGH-Z[10, 11] 18 ns
Write Cycle[12]
tWC Write Cycle Time 45 ns
tSCE CE LOW to Write End 35 ns
tAW Address Setup to Write End 35 ns
tHA Address Hold from Write End 0 ns
tSA Address Setup to Write Start 0 ns
tPWE WE Pulse Width 35 ns
tBW BLE/BHE LOW to Write End 35 ns
tSD Data Setup to Write End 25 ns
tHD Data Hold from Write End 0 ns
tHZWE WE LOW to High-Z[10, 11] 18 ns
tLZWE WE HIGH to Low-Z[10] 10 ns
Notes
9. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to
3V, and output loading of the specified IOL/IOH as shown in the AC Test Loads and Waveforms on page 4.
10.At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
11. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state.
12.The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE or both = VIL. All signals must be active to initiate a write and any of these
signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
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