CY62146EV30 MoBL®
Document #: 38-05567 Rev. *C Page 2 of 12
Logic Block Diagram
Pin Configurations [3, 4]
256K x 16
RAM Array IO0–IO7
ROW DECODER
A8
A7
A6
A5
A2
COLUMN DECODER
A11
A12
A13
A14
A15
SENSE AMPS
DATA IN DRIVERS
OE
A4
A3IO8–IO15
CE
WE
BHE
A16
A0
A1
A9
A10
BLE
A17
1
2
3
4
5
6
7
8
9
11
14 31
32
36
35
34
33
37
40
39
38
12
13
41
44
43
42
16
15
29
30
A
5
18
17
20
19
27
28
25
26
22
21
23
24
A
6
A
7
A
4
A
3
A
2
A
1
A
0
A
15
A
16
A
8
A
9
A
10
A
11
A
13
A
14
A
12
OE
BHE
BLE
CE
WE
IO
0
IO
1
IO
2
IO
3
IO
4
IO
5
IO
6
IO
7
IO
8
IO
9
IO
10
IO
11
IO
12
IO
13
IO
14
IO
15
V
CC
V
CC
V
SS
V
SS
NC
10
A
17
48-ball VFBGA
44-pin TSOP II
Top Vi ew Top Vi ew
WE
A11
A10
A6
A0
A3CE
IO10
IO8
IO9
A4
A5
IO11
IO13
IO12
IO14
IO15
VSS
A9
A8
OE
A7
IO0
BHE
NC
A2
A1
BLE
IO2
IO1
IO3
IO4
IO5IO6
IO7
A15
A14
A13
A12
NC
NC NC
326
5
41
D
E
B
A
C
F
G
H
A16
NC
VCC
VCC VSS
A17
Notes:
3. NC pins are not connected on the die.
4. Pins H1, G2, and H6 in the BGA package are address expansion pins for 8 Mb, 16 Mb and 32 Mb, respectively.