Cypress CY62146EV30 Switching Waveforms

CY62146EV30 MoBL®

Document #: 38-05567 Rev. *C Page 7 of 12

Write Cycle No. 1 (WE Controlled) [15, 19, 20]

Write Cycle No. 2 (CE Controlled) [15, 19, 20]

Switching Waveforms (continued)

tHD

tSD

tPWE

tSA

tHA

tAW

tWC

tHZOE

DATAIN

NOTE 21

tBW

tSCE

DATA IO

ADDRESS

BHE/BLE

tHD

tSD

tPWE

tHA

tAW

tSCE

tWC

tHZOE

DATAIN

tBW

tSA

ADDRESS

DATA IO

BHE/BLE

NOTE 21

Notes:

19.Data IO is high impedance if OE = VIH.

20.If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.

21.During this period, the IOs are in output state and input signals must not be applied.

Contents

Main CY62146EV30 MoBL 4-Mbit (256K x 16) Static RAM Features Functional Description Product Portfolio CY62146EV30 MoBL Document #: 38-05567 Rev. *C Page 2 of 12 Logic Block Diagram 48-ball VFBGA Pin Configurations CY62146EV30 MoBL Maximum Ratings Operating Range Electrical Characteristics CY62146EV30 MoBL Capacitance Thermal Resistance AC Test Loads and Waveforms Data Retention Characteristics Switching Characteristics CY62146EV30 MoBL Document #: 38-05567 Rev. *C Page 6 of 12 Switching Waveforms PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled) [17, 18] Switching Waveforms Document #: 38-05567 Rev. *C Page 8 of 12 Write Cycle No. 3 (WE Controlled, OE LOW) [20] Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) [20] Truth Table Ordering Information Document #: 38-05567 Rev. *C Page 10 of 12 Package Diagrams 51-85150-*D Figure 1. 48-ball VFBGA (6 x 8 x 1 mm), 51-85150 Page Document History Page