Cypress CY62146EV30 manual Maximum Ratings, Electrical Characteristics Over the Operating Range

CY62146EV30 MoBL®

Maximum Ratings

Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested.

Storage Temperature	–65°C to + 150°C
Ambient Temperature with
Power Applied	–55°C to + 125°C
Supply Voltage to Ground
Potential	–0.3V to + 3.9V	(VCCmax + 0.3V)
DC Voltage Applied to Outputs
in High-Z State [5, 6]	–0.3V to 3.9V	(V	CCmax	+ 0.3V)

Electrical Characteristics (Over the Operating Range)

DC Input Voltage [5, 6]		–0.3V to 3.9V (V		CC max		+ 0.3V)
Output Current into Outputs (LOW)						20 mA
Static Discharge Voltage						>2001V
(per MIL-STD-883, Method 3015)
Latch-up Current	.....................................................				>200 mA
Operating Range
			Ambient		VCC [7]
Device	Range		Temperature
CY62146EV30	Industrial		–40°C to +85°C		2.2V to 3.6V

45 ns

Parameter

Description

Test Conditions

Min

Typ [2]

Max

Unit

VOH

Output HIGH Voltage

IOH = –0.1 mA

2.0

V

IOH = –1.0 mA, VCC > 2.70V

2.4

V

VOL

Output LOW Voltage

IOL = 0.1 mA

0.4

V

IOL = 2.1 mA, VCC > 2.70V

0.4

V

VIH

Input HIGH Voltage

VCC = 2.2V to 2.7V

1.8

VCC + 0.3

V

VCC= 2.7V to 3.6V

2.2

VCC + 0.3

V

VIL

Input LOW Voltage

VCC = 2.2V to 2.7V

–0.3

0.6

V

VCC= 2.7V to 3.6V

–0.3

0.8

V

IIX

Input Leakage Current

GND < VI < VCC

–1

+1

∝A

IOZ

Output Leakage Current

GND < VO < VCC, Output Disabled

–1

+1

∝A

ICC

VCC Operating Supply Current

f = fmax = 1/tRC

VCC = VCC(max),

15

20

mA

IOUT = 0 mA

f = 1 MHz

2

2.5

CMOS levels

ISB1

Automatic CE Power down

> VCC−0.2V,

1

7

∝A

CE

Current — CMOS Inputs

VIN > VCC–0.2V or VIN < 0.2V

f = fmax (Address and Data Only),

f = 0 (OE,

and

BHE,

BLE

WE), VCC = 3.60V

ISB2 [8]

Automatic CE Power down

> VCC – 0.2V,

1

7

∝A

CE

Current — CMOS Inputs

VIN > VCC – 0.2V or VIN < 0.2V,

f = 0, VCC = 3.60V

Notes:

5.VIL(min) = –2.0V for pulse durations less than 20 ns.

6.VIH(max) = VCC + 0.75V for pulse durations less than 20 ns.

7.Full device AC operation assumes a minimum of 100 ∝s ramp time from 0 to Vcc(min) and 200 ∝s wait time after Vcc stabilization.

8.Only chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be left floating.

Document #: 38-05567 Rev. *C Page 3 of 12