Cypress CY7C1338G manual Features, Functional Description1, Logic Block Diagram

CY7C1338G

4-Mbit (128K x 32) Flow-Through Sync SRAM

Features

•128K x 32 common I/O

•3.3V core power supply (VDD)

•2.5V or 3.3V I/O supply (VDDQ)

•Fast clock-to-output times

— 6.5 ns (133-MHz version)

•Provide high-performance 2-1-1-1 access rate

•User-selectable burst counter supporting Intel→ Pentium→ interleaved or linear burst sequences

•Separate processor and controller address strobes

•Synchronous self-timed write

•Asynchronous output enable

•Offered in lead-free 100-Pin TQFP package, lead-free and non-lead-free 119-Ball BGA package

•“ZZ” Sleep Mode option

Functional Description[1]

The CY7C1338G is a 128K x 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is

6.5ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automati- cally for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables

(BW[A:D], and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin.

The CY7C1338G allows either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe (ADSP) or the cache Controller Address Strobe (ADSC) inputs. Address advancement is controlled by the Address Advancement (ADV) input.

Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV).

The CY7C1338G operates from a +3.3V core power supply while all outputs may operate with either a +2.5 or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible.

Logic Block Diagram
A0, A1, A			ADDRESS
			REGISTER
MODE				A[1:0]
ADV			BURST	Q1
CLK			COUNTER
			AND LOGIC
		CLR		Q0
ADSC
ADSP
		DQD BYTE		DQD BYTE
BWD				WRITE REGISTER
		WRITE REGISTER
		DQC BYTE		DQC BYTE
BWC				WRITE REGISTER
		WRITE REGISTER
					MEMORY	SENSE	OUTPUT	DQs
					ARRAY		BUFFERS
				DQB BYTE		AMPS
		DQB BYTE
BWB				WRITE REGISTER
		WRITE REGISTER
				DQA BYTE
BWA		DQA BYTE		WRITE REGISTER
		WRITE REGISTER
BWE
GW							INPUT
CE1		ENABLE					REGISTERS
		REGISTER
CE2
CE3
OE
ZZ	SLEEP
	CONTROL
Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Cypress Semiconductor Corporation	•	198 Champion Court • San Jose, CA 95134-1709	•	408-943-2600
Document #: 38-05521 Rev. *D		Revised July 5, 2006