CY7C1338G
Document #: 38-05521 Rev. *D Page 3 of 17
Pin Definitions
Name I/O Description
A0, A1, A Input-
Synchronous Address Inputs used to select one of the 128K address locations. Sampled at the rising edge
of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed
the 2-bit counter.
BWA, BWB
BWC, BWD
Input-
Synchronous Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Sampled on the rising edge of CLK.
GW Input-
Synchronous Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global
write is conducted (ALL bytes are written, regardless of the values on BW[A:D] and BWE).
BWE Input-
Synchronous Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be
asserted LOW to conduct a byte write.
CLK Input-Clock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
CE1Input-
Synchronous Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only
when a new external address is loaded.
CE2Input-
Synchronous Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE3 to select/deselect the device. CE2 is sampled only when a new external address is
loaded.
CE3Input-
Synchronous Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE2 to select/deselect the device. CE3 is sampled only when a new external address is
loaded.
OE Input-
Asynchronous Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When
LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as
input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected
state.
ADV Input-
Synchronous Advance Input signal, sampled on the rising edge of CLK. When asserted, it automatically
increments the address in a burst cycle.
Pin Configurations (continued)
2345671
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC/288M
NC/144M
NCDQ
C
DQ
D
DQ
C
DQ
D
AA AA
ADSP V
DDQ
CE
2
A
DQ
C
V
DDQ
DQ
C
V
DDQ
V
DDQ
V
DDQ
DQ
D
DQ
D
NC
NC
V
DDQ
V
DD
CLK
V
DD
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC/576M
NC/1G
NC
NC
NCNCNCNC
NC/36MNC/72M
NC
V
DDQ
V
DDQ
V
DDQ
AAA
A
NC/9M
AA
A
AA
A
A0
A1
DQ
A
DQ
C
DQ
A
DQ
A
DQ
A
DQ
B
DQ
B
DQ
B
DQ
B
DQ
B
DQ
B
DQ
B
DQ
A
DQ
A
DQ
A
DQ
A
DQ
B
V
DD
DQ
C
DQ
C
DQ
C
V
DD
DQ
D
DQ
D
DQ
D
DQ
D
ADSC
NC
CE
1
OE
ADV
GW
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
MODE
NC
NC
BW
B
BW
C
NC V
DD
NC
BW
A
NC
BWE
BW
D
ZZ

119-Ball BGA Pinout

A