Cypress CY7C1338G manual Read/Write Timing17, 19, DON’T Care

Models: CY7C1338G

1 17

Page 13

CY7C1338G

tCYC

CLK

CH CL

BWE, BW[A:D]

tCES tCEH

A5 A6

tOELZ

tCDV

Q(A4) Q(A4+1) Q(A4+2) Q(A4+3)

BURST READ

D(A5) D(A6)

Back-to-Back

WRITEs

UNDEFINED

Notes:

19.The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.

20.GW is HIGH.

Document #: 38-05521 Rev. *D

Page 13 of 17

Image 13

Contents

Logic Block Diagram FeaturesFunctional Description1 Cypress Semiconductor CorporationSelection Guide Pin Configurations15CY7C1338G 133 MHz 100 MHz UnitPin Definitions Pin Configurations Ball BGA PinoutName Description Byte Write Select Inputs, active LOW. Qualified withFunctional Overview Linear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics CE2 Adsp Adsc ADV Write CLK Address Cycle Description UsedFunction Partial Truth Table for Read/Write2Operating Range Maximum RatingsAmbient Range GND ≤ VI ≤ VddqThermal Resistance10 Capacitance10AC Test Loads and Waveforms 133 100 Parameter Description Unit Min Max Setup TimesClock Output TimesRead Cycle Timing17 Timing DiagramsAdsc Write Cycle Timing17DON’T Care Read/Write Timing17, 19ZZ Mode Timing 21 Ordering Information Package DiagramsPin Tqfp 14 x 20 x 1.4 mm Ball BGA 14 x 22 x 2.4 mm Document History Issue Date Orig. Description of Change