Cypress CY7C1338G Timing Diagrams

CY7C1338G

Document #: 38-05521 Rev. *D Page 11 of 17

Timing Diagrams

Read Cycle Timing[17]

Note:

17.On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

tCYC

tCL

CLK

tADH

tADS

ADDRESS

tCH

tAH

tAS

tCEH

tCES

Data Out (Q) High-Z

tCLZ

tDOH

tCDV

tOEHZ

tCDV

Single READ

BURST

READ

tOEV tOELZ tCHZ

Burst wraps around

to its initial state

tADVH

tADVS

tWEH

tWES

tADH

tADS

Q(A2)

Q(A2 + 1)

Q(A2 + 2)

Q(A1) Q(A2)

Q(A2 + 1)

Q(A2 + 2)

Q(A2 + 3)

ADV suspends burst.

Deselect Cycle

DON’T CARE UNDEFINED

ADSP

ADSC

W, BWE,BW

[A:D]

ADV

Contents

Main 4-Mbit (128K x 32) Flow-Through Sync SRAM CY7C1338G Logic Block Diagram Features Functional Description CY7C1338G Pin Configurations 100-Pin TQFP Pinout CY7C1338G Pin Definitions Pin Configurations 119-Ball BGA Pinout Functional Overview Pin Definitions Interleaved Burst Address Table (MODE = Floating or VDD) Linear Burst Address Table (MODE = GND) ZZ Mode Electrical Characteristics Truth Table CY7C1338G Partial Truth Table for Read/Write CY7C1338G Maximum Ratings Operating Range Electrical Characteristics Capacitance Thermal Resistance AC Test Loads and Waveforms Switching Characteristics Timing Diagrams Read Cycle Timing Write Cycle Timing CY7C1338G Read/Write Timing ZZ Mode Timing Ordering Information Package Diagrams A Package Diagrams 119-Ball BGA (14 x 22 x 2.4 mm) (51-85115) 51-85115-*B 0.56 0.900.05 Document History Page