Timing Diagrams, Read Cycle Timing17 | Cypress CY7C1338G instruction

CY7C1338G

Timing Diagrams

tCYC

CLK

t CH

tADS tADH

ADSP

ADSC

tAS tAH

t CL

tADS tADH

ADDRESS

GW, BWE,BW[A:D]

tCDV

Single READ

ADV suspends burst.

UNDEFINED

Note:

17. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

Document #: 38-05521 Rev. *D

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Contents

Cypress Semiconductor Corporation FeaturesLogic Block Diagram Functional Description1 133 MHz 100 MHz Unit Pin ConfigurationsSelection Guide 15CY7C1338G Byte Write Select Inputs, active LOW. Qualified with Pin Configurations Ball BGA PinoutPin Definitions Name Description Functional Overview ZZ Mode Electrical Characteristics Interleaved Burst Address Table Mode = Floating or VDDLinear Burst Address Table Mode = GND CE2 Adsp Adsc ADV Write CLK Address Cycle Description Used Function Partial Truth Table for Read/Write2 GND ≤ VI ≤ Vddq Maximum RatingsOperating Range Ambient Range AC Test Loads and Waveforms Capacitance10Thermal Resistance10 Output Times Setup Times133 100 Parameter Description Unit Min Max Clock Read Cycle Timing17 Timing Diagrams Adsc Write Cycle Timing17 DON’T Care Read/Write Timing17, 19 ZZ Mode Timing 21 Pin Tqfp 14 x 20 x 1.4 mm Package DiagramsOrdering Information Ball BGA 14 x 22 x 2.4 mm Document History Issue Date Orig. Description of Change