ZZ Mode Timing 21 | Cypress CY7C1338G guide

CY7C1338G

ZZMode Timing [21, 22]

CLK

tZZ

tZZI

ISUPPLY

I DDZZ

ALL INPUTS (except ZZ)

Outputs (Q)

High-Z

tZZREC

tRZZI

DESELECT or READ Only

Notes:

21.Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.

22.DQs are in high-Z when exiting ZZ sleep mode.

Document #: 38-05521 Rev. *D

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Contents

Functional Description1 FeaturesLogic Block Diagram Cypress Semiconductor Corporation 15CY7C1338G Pin ConfigurationsSelection Guide 133 MHz 100 MHz Unit Name Description Pin Configurations Ball BGA PinoutPin Definitions Byte Write Select Inputs, active LOW. Qualified with Functional Overview ZZ Mode Electrical Characteristics Interleaved Burst Address Table Mode = Floating or VDDLinear Burst Address Table Mode = GND Address Cycle Description Used CE2 Adsp Adsc ADV Write CLK Partial Truth Table for Read/Write2 Function Ambient Range Maximum RatingsOperating Range GND ≤ VI ≤ Vddq AC Test Loads and Waveforms Capacitance10Thermal Resistance10 Clock Setup Times133 100 Parameter Description Unit Min Max Output Times Timing Diagrams Read Cycle Timing17 Write Cycle Timing17 Adsc Read/Write Timing17, 19 DON’T Care ZZ Mode Timing 21 Pin Tqfp 14 x 20 x 1.4 mm Package DiagramsOrdering Information Ball BGA 14 x 22 x 2.4 mm Issue Date Orig. Description of Change Document History