Cypress CY7C1338G ZZ Mode Timing

CY7C1338G

Document #: 38-05521 Rev. *D Page 14 of 17

ZZ Mode Timing [21, 22]

Notes:

21.Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.

22.DQs are in high-Z when exiting ZZ sleep mode.

Timing Diagrams (continued)

tZZ

SUPPLY

CLK

tZZREC

LL INPUTS

(except ZZ)

DON’T CARE

IDDZZ

tZZI

tRZZI

Outputs (Q)

High-Z

DESELECT or READ Only

Contents

Main 4-Mbit (128K x 32) Flow-Through Sync SRAM CY7C1338G Logic Block Diagram Features Functional Description CY7C1338G Pin Configurations 100-Pin TQFP Pinout CY7C1338G Pin Definitions Pin Configurations 119-Ball BGA Pinout Functional Overview Pin Definitions Interleaved Burst Address Table (MODE = Floating or VDD) Linear Burst Address Table (MODE = GND) ZZ Mode Electrical Characteristics Truth Table CY7C1338G Partial Truth Table for Read/Write CY7C1338G Maximum Ratings Operating Range Electrical Characteristics Capacitance Thermal Resistance AC Test Loads and Waveforms Switching Characteristics Timing Diagrams Read Cycle Timing Write Cycle Timing CY7C1338G Read/Write Timing ZZ Mode Timing Ordering Information Package Diagrams A Package Diagrams 119-Ball BGA (14 x 22 x 2.4 mm) (51-85115) 51-85115-*B 0.56 0.900.05 Document History Page