Cypress CY7C1338G Write Cycle Timing

CY7C1338G

Document #: 38-05521 Rev. *D Page 12 of 17

Write Cycle Timing[17, 18]

Note:

18.Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A:D] LOW.

Timing Diagrams (continued)

tCYC

tCL

CLK

tADH

tADS

ADDRESS

tCH

tAH

tAS

tCEH

tCES

High-Z

BURST READ BURST WRITE

D(A2)

D(A2 + 1)

D(A1) D(A3)

D(A3 + 1)

D(A3 + 2)

D(A2 + 3)

A2 A3

Extended BURST WRITE

D(A2 + 2)

Single WRITE

tADH

tADS

tADH

tADS

tOEHZ

tADVH

tADVS

tWEH

tWES

tDH

tDS

tWEH

tWES

Byte write signals are ignored for first cycle when

ADSP initiates burst

ADSC extends burst

ADV suspends burst

DON’T CARE UNDEFINED

ADSP

ADSC

BWE,

BW[A:D]

ADV

Data in (D)

ata Out (Q)

Contents

Main 4-Mbit (128K x 32) Flow-Through Sync SRAM CY7C1338G Logic Block Diagram Features Functional Description CY7C1338G Pin Configurations 100-Pin TQFP Pinout CY7C1338G Pin Definitions Pin Configurations 119-Ball BGA Pinout Functional Overview Pin Definitions Interleaved Burst Address Table (MODE = Floating or VDD) Linear Burst Address Table (MODE = GND) ZZ Mode Electrical Characteristics Truth Table CY7C1338G Partial Truth Table for Read/Write CY7C1338G Maximum Ratings Operating Range Electrical Characteristics Capacitance Thermal Resistance AC Test Loads and Waveforms Switching Characteristics Timing Diagrams Read Cycle Timing Write Cycle Timing CY7C1338G Read/Write Timing ZZ Mode Timing Ordering Information Package Diagrams A Package Diagrams 119-Ball BGA (14 x 22 x 2.4 mm) (51-85115) 51-85115-*B 0.56 0.900.05 Document History Page