Cypress CY7C1338G manual Write Cycle Timing17, Adsc

CY7C1338G

Timing Diagrams (continued)

Write Cycle Timing[17, 18]

tCYC

CLK

tCH tCL

tADS tADH

ADSP

tADS tADH

ADSC

tAS tAH

ADDRESS A1 A2

Byte write signals are ignored for first cycle when

ADSP initiates burst

BWE,

BW[A:D]

t t

WES WEH

ADSC extends burst

tADS tADH

A3

tWES tWEH

GW

tCES tCEH

CE

tADVS tADVH

ADV

OE

Data in (D) High-Z

Data Out (Q)

tOEHZ

tDS t DH

D(A1)

ADV suspends burst

D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2)

BURST READ Single WRITE

BURST WRITE

Extended BURST WRITE

DON’T CARE UNDEFINED

Note:

18. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A:D] LOW.

Document #: 38-05521 Rev. *D Page 12 of 17