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Cypress CY62147DV30 Document #: 38-05340 Rev. *F Page 8 of 12, Write Cycle No. 3 (WE Controlled, OE LOW)[22], Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[22]

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CY62147DV30

Document #: 38-05340 Rev. *F Page 8 of 12

Write Cycle No. 3 (WE Controlled, OE LOW)[22]

Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[22]

Switching Waveforms (continued)

DATAIN

tHD

tSD

tLZWE

tPWE

tSA

tHA

tAW

tSCE

tWC

tHZWE

ADDRESS

DATAI/O NOTE 23

tBW

BHE/BLE

DATA I/O

ADDRESS

tWC

DATA

NOTE 23

BHE/BLE

tSCE

PWE

tHZWE tHD

tLZWE

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Contents

Main 4-Mbit (256K x 16) Static RAM CY62147DV30 Features Functional Description Logic Block Diagram CY62147DV30 Document #: 38-05340 Rev. *F Page 2 of 12 Pin Configuration (ns) Product VCC Range (V) Speed CY62147DV30 Maximum Ratings Operating Range Electrical Characteristics CY62147DV30 Capacitance Thermal Resistance AC Test Loads and Waveforms Data Retention Characteristics Switching Characteristics CY62147DV30 Switching Waveforms Read Cycle 1 (Address Transition Controlled) Read Cycle No. 2 (OE Controlled)[19, 20] ADDRESS DATA OUT PREVIOUS DATA VALID DATA VALID CY62147DV30 Write Cycle No. 1 (WE Controlled)[17, 21, 22] Write Cycle No. 2 (CE Controlled)[17, 21, 22] Switching Waveforms t Document #: 38-05340 Rev. *F Page 8 of 12 Write Cycle No. 3 (WE Controlled, OE LOW)[22] Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[22] Truth Table Ordering Information Package Diagram 48-ball VFBGA (6 x 8 x 1 mm) (51-85150) 51-85150-*D Page Document History Page