CY62147DV30
Document #: 38-05340 Rev. *F Page 5 of 12
Switching Characteristics Over the Operating Range[14]
Parameter Description
45 ns[11] 55 ns 70 ns
UnitMin. Max. Min. Max. Min. Max.
Read Cycle
tRC Read Cycle Time 45 55 70 ns
tAA Address to Data Valid 45 55 70 ns
tOHA Data Hold from Address Change 10 10 10 ns
tACE CE LOW to Data Valid 45 55 70 ns
tDOE OE LOW to Data Valid 25 25 35 ns
tLZOE OE LOW to LOW Z[15] 5 5 5 ns
tHZOE OE HIGH to High Z[15, 16] 15 20 25 ns
tLZCE CE LOW to Low Z[15] 10 10 10 ns
tHZCE CE HIGH to High Z[15, 16] 20 20 25 ns
tPU CE LOW to Power-Up 0 0 0 ns
tPD CE HIGH to Power-Down 45 55 70 ns
tDBE BLE/BHE LOW to Data Valid 45 55 70 ns
tLZBE BLE/BHE LOW to Low Z[15] 10 10 10 ns
tHZBE BLE/BHE HIGH to HIGH Z[15, 16] 15 20 25 ns
Write Cycle[17]
tWC Write Cycle Time 45 55 70 ns
tSCE CE LOW to Write End 40 40 60 ns
tAW Address Set-up to Write End 40 40 60 ns
tHA Address Hold from Write End 0 0 0 ns
tSA Address Set-up to Write Start 0 0 0 ns
tPWE WE Pulse Width 35 40 45 ns
tBW BLE/BHE LOW to Write End 40 40 60 ns
tSD Data Set-up to Write End 25 25 30 ns
tHD Data Hold from Write End 0 0 0 ns
tHZWE WE LOW to High-Z[15, 16] 15 20 25 ns
tLZWE WE HIGH to Low-Z[15] 10 10 10 ns
Notes:
14.Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1 V/ns) or less, timing reference levels of VCC(typ)/2, input
pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section.
15.At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any
given device.
16.tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedence state.
17.The internal Write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
the write.
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