Cypress CY62147DV30 CY62147DV30

CY62147DV30

Document #: 38-05340 Rev. *F Page 7 of 12

Write Cycle No. 1 (WE Controlled)[17, 21, 22]

Write Cycle No. 2 (CE Controlled)[17, 21, 22]

Notes:

21.Data I/O is high impedance if OE = VIH.

22.If CE goes HIGH simultaneously with WE = VIH, the output remains in a high-impedance state.

23.During this period, the I/Os are in output state and input signals should not be applied.

Switching Waveforms (continued)

tHD

tSD

tPWE

tSA

tHA

tAW

tWC

DATA I/O

ADDRESS

tHZOE

DATAIN

NOTE23

BHE/BLE tBW

tSCE

tHD

tSD

tPWE

tHA

tAW

tSCE

tWC

tHZOE

DATAIN

ADDRESS

DATA I/O

NOTE23

BHE/BLE tBW

tSA

[+] Feedback

Contents

Main 4-Mbit (256K x 16) Static RAM CY62147DV30 Features Functional Description Logic Block Diagram CY62147DV30 Document #: 38-05340 Rev. *F Page 2 of 12 Pin Configuration (ns) Product VCC Range (V) Speed CY62147DV30 Maximum Ratings Operating Range Electrical Characteristics CY62147DV30 Capacitance Thermal Resistance AC Test Loads and Waveforms Data Retention Characteristics Switching Characteristics CY62147DV30 Switching Waveforms Read Cycle 1 (Address Transition Controlled) Read Cycle No. 2 (OE Controlled)[19, 20] ADDRESS DATA OUT PREVIOUS DATA VALID DATA VALID CY62147DV30 Write Cycle No. 1 (WE Controlled)[17, 21, 22] Write Cycle No. 2 (CE Controlled)[17, 21, 22] Switching Waveforms t Document #: 38-05340 Rev. *F Page 8 of 12 Write Cycle No. 3 (WE Controlled, OE LOW)[22] Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[22] Truth Table Ordering Information Package Diagram 48-ball VFBGA (6 x 8 x 1 mm) (51-85150) 51-85150-*D Page Document History Page