CY62147DV30
Document #: 38-05340 Rev. *F Page 4 of 12
Notes:
10.Tested initially and after any design or process changes that may affect these parameters.
11.Test condition for the 45-ns part is a load capacitance of 30 pF.
12.Full device operation requires linear VCC ramp from VDR to VCC(min.) > 100 µs or stable at VCC(min.) > 100 µs.
13.BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
Capacitance (for all packages)[10]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
VCC = VCC(typ)
10 pF
COUT Output Capacitance 10 pF
Thermal Resistance[10]
Parameter Description Test Conditions VFBGA TSOP II Unit
ΘJA Thermal Resistance
(Junction to Ambient) Still Air, soldered on a 3 × 4.5 inch, four-layer
printed circuit board 72 75.13 °C/W
ΘJC Thermal Resistance
(Junction to Case) 8.86 8.95 °C/W
AC Test Loads and Waveforms[10]
Parameters 2.50V 3.0V Unit
R1 16667 1103 Ω
R2 15385 1554 Ω
RTH 8000 645 Ω
VTH 1.20 1.75 V
Data Retention Characteristics (Over the Operating Range)
Parameter Description Conditions Min. Ty p.[5] Max. Unit
VDR VCC for Data Retention 1.5 V
ICCDR Data Retention Current VCC= 1.5V
CE > VCC – 0.2V,
VIN > VCC – 0.2V or
VIN < 0.2V
L (Auto-E) 15 µA
LL (Ind’l/Auto-A) 6
tCDR[10] Chip Deselect to Data Retention
Time 0ns
tR[12] Operation Recovery Time tRC ns
VCC VCC
OUTPUT
R2
50 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10% 90%
10%
Rise Time = 1 V/ns Fall Time = 1 V/ns
OUTPUT V
Equivalent to: THÉ VENIN EQUIVALENT
ALL INPUT PULSES
RTH
R1
Data Retention Waveform[13]
VCC(min)
VCC(min)
tCDR
VDR>1.5 V
DATA RETENTION MODE
tR
VCC
CE or
BHE.BLE
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