Cypress CY62167EV18 CY62167EV18 MoBL

CY62167EV18 MoBL®

Document #: 38-05447 Rev. *G Page 6 of 13

Switching Waveforms

Figure 4 shows address transition controlled read cycle waveforms.[18, 19]

Figure 4. Read Cycle No. 1

Figure 5 shows OE controlled read cycle waveforms.[19, 20]

Figure 5. Read Cycle No. 2

PREVIOUS DATA VALID DATA VALID

tAA

tOHA

tRC

ADDRESS

DATA OUT

50%

DATA VALID

tRC

tACE

tDOE

tLZOE

tLZCE

tPU

HIGH IMPEDANCE

tHZOE

tPD

tHZBE

tLZBE

HZCE

tDBE

CE1

ADDRESS

CE2

BHE/BLE

DATA OUT

VCC

SUPPLY

CURRENT

HIGH

ICC

ISB

IMPEDANCE

Notes

18.The device is continuously selected. OE, CE1 = VIL, BHE, BLE or both = VIL, and CE2 = VIH.

19.WE is HIGH for read cycle.

20.Address valid before or similar to CE1, BHE, BLE transition LOW and CE2 transition HIGH.

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Contents

Main CY62167EV18 MoBL 16 Mbit (1M x 16) Static RAM Features Functional Description Logic Block Diagram CY62167EV18 MoBL Pin Configuration Figure 1. 48-Ball VFBGA (6 x 7 x 1mm) / (6 x 8 x 1mm) Top View Product Portfolio Product VCC Range (V) Speed (ns) Maximum Ratings Operating Range Electrical Characteristics Capacitance Thermal Resistance Data Retention Characteristics Switching Characteristics CY62167EV18 MoBL Switching Waveforms Figure 5 shows OE controlled read cycle waveforms.[19, 20] Figure 5. Read Cycle No. 2 CY62167EV18 MoBL Document #: 38-05447 Rev. *G Page 7 of 13 Figure 6 shows WE controlled write cycle waveforms.[17, 21, 22] Figure 6. Write Cycle No. 1 CY62167EV18 MoBL Document #: 38-05447 Rev. *G Page 8 of 13 t Figure 7 shows CE1 or CE2 controlled write cycle waveforms.[17, 21, 22] Figure 7. Write Cycle No. 2 Figure 8 shows WE controlled, OE LOW write cycle waveforms.[22] Figure 8. Write Cycle No. 3 Truth Table Ordering Information Package Diagram Figure 11. 48-Ball VFBGA (6 x 8 x 1 mm), 51-85150 Package Diagram 51-85150-*D Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC Solutions