Cypress CY62167EV18 CY62167EV18 MoBL

CY62167EV18 MoBL®

Document #: 38-05447 Rev. *G Page 7 of 13

Figure 6 shows WE controlled write cycle waveforms.[17, 21, 22]

Figure 6. Write Cycle No. 1

Switching Waveforms (continued)

tHD

tSD

tPWE

tSA

tHA

tAW

tSCE

tWC

tHZOE

VALID DATA

tBW

NOTE 23

CE1

ADDRESS

CE2

DATA I/O

BHE/BLE

Notes

21.Data IO is high impedance if OE = VIH.

22.If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state.

23.During this period the IOs are in output state. Do not apply input signals.

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Contents

Main CY62167EV18 MoBL 16 Mbit (1M x 16) Static RAM Features Functional Description Logic Block Diagram CY62167EV18 MoBL Pin Configuration Figure 1. 48-Ball VFBGA (6 x 7 x 1mm) / (6 x 8 x 1mm) Top View Product Portfolio Product VCC Range (V) Speed (ns) Maximum Ratings Operating Range Electrical Characteristics Capacitance Thermal Resistance Data Retention Characteristics Switching Characteristics CY62167EV18 MoBL Switching Waveforms Figure 5 shows OE controlled read cycle waveforms.[19, 20] Figure 5. Read Cycle No. 2 CY62167EV18 MoBL Document #: 38-05447 Rev. *G Page 7 of 13 Figure 6 shows WE controlled write cycle waveforms.[17, 21, 22] Figure 6. Write Cycle No. 1 CY62167EV18 MoBL Document #: 38-05447 Rev. *G Page 8 of 13 t Figure 7 shows CE1 or CE2 controlled write cycle waveforms.[17, 21, 22] Figure 7. Write Cycle No. 2 Figure 8 shows WE controlled, OE LOW write cycle waveforms.[22] Figure 8. Write Cycle No. 3 Truth Table Ordering Information Package Diagram Figure 11. 48-Ball VFBGA (6 x 8 x 1 mm), 51-85150 Package Diagram 51-85150-*D Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC Solutions