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Cypress CY7C1277V18, CY7C1270V18 manual Switching Waveforms, Read/Write/Deselect Sequence29, Nop

Models: CY7C1270V18 CY7C1277V18 CY7C1266V18 CY7C1268V18

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CY7C1266V18, CY7C1277V18

CY7C1268V18, CY7C1270V18

Switching Waveforms

Read/Write/Deselect Sequence[29, 30]

Figure 5. Waveform for 2.5 Cycle Read Latency

NOP

tKH

	READ	READ	NOP	NOP	NOP	WRITE	WRITE	READ	NOP	NOP
	2	3	4	5	6	7	8	9	10	11	12
tKL	tCYC	tKHKH

K
LD
	tSC	tHC
R/W
A	A0		A1	A2	A3	A4
A				tQVLD
	tSA	tHA	tQVLD	tQVLD		tQVLD
	tSA	tHA	tQVLD			tQVLD

QVLD				tHD		tHD
				tHD	tSD	tHD
		Q01 Q10		tSD	tSD
DQ	Q00	Q01 Q10		Q11	D20 D21	D30 D31	Q40
DQ		tDOH
	tCLZ	tDOH		tCHZ
	tCO			tCQD
	(Read Latency = 2.5 Cycles)			tCQDOH
	tCCQO			tCQDOH
	tCQOH
CQ		t			tCQH	tCQHCQH
		t	CCQO		tCQH	tCQHCQH
	tCQOH		CCQO
	tCQOH
CQ
						DON’T CARE	UNDEFINED

Notes

29.Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0 + 1.

30.Outputs are disabled (High-Z) one clock cycle after a NOP.

Document Number: 001-06347 Rev. *D

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Cypress CY7C1277V18, CY7C1270V18, CY7C1266V18, CY7C1268V18 manual Switching Waveforms, Read/Write/Deselect Sequence29, Nop

Contents

Selection Guide FeaturesConfigurations Functional Description Logic Block Diagram CY7C1277V18 Logic Block Diagram CY7C1266V18 Logic Block Diagram CY7C1270V18 Logic Block Diagram CY7C1268V18 TMS TDI Pin ConfigurationsCY7C1266V18 4M x CY7C1277V18 4M x BWS CY7C1268V18 2M xCY7C1270V18 1M x Qvld Negative Input Clock Input Pin DefinitionsPin Name Pin Description Synchronous Read/Write Input. When TCK Pin for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TDO for Jtag Functional Overview Operation Delay Lock Loop DLLApplication Example Truth Table During the data portion of a write sequence Write Cycle DescriptionsComments Remains unaltered Into the device. D 80 and D 3518 remain unaltered Write cycle description table for CY7C1270V18 follows.2Into the device Written into the device. D 359 remains unaltered Ieee 1149.1 Serial Boundary Scan Jtag Idcode State diagram for the TAP controller follows.9 TAP Controller State Diagram GND ≤ VI ≤ VDD TAP Controller Block DiagramTAP Electrical Characteristics Parameter Description Test Conditions Min Max Unit TAP Timing and Test Conditions TAP AC Switching Characteristics Register Name Bit Size Identification Register DefinitionsScan Register Sizes Instruction Codes Bit # Bump ID Boundary Scan Order DLL Constraints Power Up Sequence in DDR-II+ SramPower Up Sequence Power Up Waveforms Operating Range Electrical CharacteristicsDC Electrical Characteristics Maximum Ratings Parameter Description Test Conditions Max Unit Capacitance20Thermal Resistance20 AC Test Loads and Waveforms LOW Switching CharacteristicsParameter Min Max High NOP Switching WaveformsRead/Write/Deselect Sequence29 Ordering Information 333 Ball Fbga 15 x 17 x 1.40 mm Package Diagram VKN ECN No Issue Date Orig. Description of ChangeDocument History NXR

Switching Waveforms

Read/Write/Deselect Sequence[29, 30]

Figure 5. Waveform for 2.5 Cycle Read Latency

NOP

READ

NOP

WRITE

tKHKH

CCQO

DON’T CARE

UNDEFINED