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Cypress CY7C1266V18, CY7C1268V18, CY7C1270V18, CY7C1277V18 Switching Waveforms

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CY7C1266V18, CY7C1277V18

CY7C1268V18, CY7C1270V18

Document Number: 001-06347 Rev. *D Page 23 of 27

Switching Waveforms

Read/Write/Deselect Sequence[29, 30]

Figure 5. Waveform for 2.5 Cycle Read Latency

12345678910

READ READ

NOP WRITEWRITE

NOP

11

R/W

tKH tKL tCYC

tHC

tSA tHA

DON’T CARE UNDEFINED

A0 A1 A2 A3 A4

QVLD

NOP

tCCQO

tCQOH

tCCQO

tCQOH

QVLD

KHKH

READ

(Read Latency = 2.5 Cycles)

NOP NOP

tCLZ tCHZ

CQDOH

Q00 Q11

Q01 Q10

tDOH

tCO

Q40

tSD

tHD

D20 D21 D30 D31

tCQD

tCQH tCQHCQH

Notes

29.Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0 + 1.

30.Outputs are disabled (High-Z) one clock cycle after a NOP.

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Contents

Main CY7C1266V18, CY7C1277V18 CY7C1268V18, CY7C1270V18 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations Functional Description Selection Guide CY7C1266V18, CY7C1277V18 CY7C1268V18, CY7C1270V18 Document Number: 001-06347 Rev. *D Page 2 of 27 Logic Block Diagram (CY7C1266V18) Logic Block Diagram (CY7C1277V18) 2M x 8 Array 2M x 8 Array Logic Block Diagram (CY7C1268V18) Logic Block Diagram (CY7C1270V18) 1M x 18 Array 1M x 18 Array 512K x 36 Array 512K x 36 Array Pin Configurations CY7C1266V18 (4M x 8) 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1277V18 (4M x 9) Pin Configurations CY7C1268V18 (2M x 18) 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1270V18 (1M x 36) CY7C1266V18, CY7C1277V18 CY7C1268V18, CY7C1270V18 Pin Definitions CY7C1266V18, CY7C1277V18 CY7C1268V18, CY7C1270V18 Pin Definitions CY7C1266V18, CY7C1277V18 CY7C1268V18, CY7C1270V18 Functional Overview Read Operations Write Operations Byte Write Operations Application Example Truth Table BUS MASTER (CPU or ASIC) SRAM#1 SRAM#2 Page Page CY7C1266V18, CY7C1277V18 CY7C1268V18, CY7C1270V18 IEEE 1149.1 Serial Boundary Scan (JTAG) Disabling the JTAG Feature Test Access Port Test Clock Test Mode Select Page TAP Controller State Diagram TAP Controller Block Diagram TAP Controller TAP Electrical Characteristics TAP AC Switching Characteristics TAP Timing and Test Conditions Test Clock Test Mode Select TCK TMS Test Data In TDI Test Data Out TDO Identification Register Definitions Scan Register Sizes Instruction Codes CY7C1266V18, CY7C1277V18 CY7C1268V18, CY7C1270V18 Boundary Scan Order Power Up Sequence in DDR-II+ SRAM Power Up Sequence Clock Start (Clock Starts after VDD/VDDQ is Stable) Fix HIGH (tie to VDDQ) DLL Constraints Maximum Ratings Operating Range Electrical Characteristics DC Electrical Characteristics AC Input Requirements Capacitance Thermal Resistance AC Test Loads and Waveforms Switching Characteristics Document Number: 001-06347 Rev. *D Page 23 of 27 Switching Waveforms Read/Write/Deselect Sequence READ READ 12345678910 Figure 5. Waveform for 2.5 Cycle Read Latency Page Ordering Information CY7C1266V18, CY7C1277V18 CY7C1268V18, CY7C1270V18 Document Number: 001-06347 Rev. *D Page 26 of 27 [+] Feedback [+] Feedback Package Diagram Figure 6. 165-ball FBGA (15 x 17 x 1.40 mm), 51-85195 CY7C1266V18, CY7C1277V18 CY7C1268V18, CY7C1270V18 Document History Page