Cypress CY7C1277V18, CY7C1266V18 Logic Block Diagram CY7C1268V18, Logic Block Diagram CY7C1270V18

CY7C1266V18, CY7C1277V18

CY7C1268V18, CY7C1270V18

Logic Block Diagram (CY7C1268V18)

A(19:0)			20
							Address
							Register
				LD
					K	CLK
					K
							Gen.
	DOFF
	VREF
							Control
		R/W
							Logic
		BWS
						[1:0]

Write	Write
Reg	Reg

Write Add. Decode	1M x 18 Array	1M x 18 Array
	Read Data Reg.
		36
		18
		18

Read Add. Decode

							18
	Output
		Logic
					R/W
	Control
				18					CQ
Reg.			Reg.					CQ
								DQ[17:0]
Reg.				18		18
								QVLD

Logic Block Diagram (CY7C1270V18)

A(18:0)			19
							Address
							Register
				LD
					K	CLK
					K
							Gen.
	DOFF
	VREF
							Control
		R/W
							Logic
		BWS
						[3:0]

Write	Write
Reg	Reg

Decode	512K x	512K x
Write Add.	36 Array	36 Array
	Read Data Reg.
		72
		36
		36

Read Add. Decode

							36
	Output
		Logic
					R/W
	Control
				36					CQ
Reg.			Reg.					CQ
								DQ[35:0]
Reg.				36		36
								QVLD

Document Number: 001-06347 Rev. *D Page 3 of 27

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