Cypress CY7C1268V18, CY7C1270V18 Logic Block Diagram CY7C1266V18, Logic Block Diagram CY7C1277V18

CY7C1266V18, CY7C1277V18

CY7C1268V18, CY7C1270V18

Logic Block Diagram (CY7C1266V18)

A(20:0)			21
							Address
							Register
				LD
					K	CLK
					K
							Gen.
	DOFF
	VREF
							Control
		R/W
							Logic
		NWS
						[1:0]

Write	Write
Reg	Reg

Write Add. Decode	2M x 8 Array	2M x 8 Array
	Read Data Reg.
		16
		8
		8

Read Add. Decode

							8
	Output
		Logic
					R/W
	Control
				8					CQ
Reg.			Reg.					CQ
				8		8		DQ[7:0]
Reg.
								QVLD

Logic Block Diagram (CY7C1277V18)

A(20:0)			21
							Address
							Register
				LD
					K	CLK
					K
							Gen.
	DOFF
	VREF
							Control
		R/W
							Logic
		BWS
						[0]

Write	Write
Reg	Reg

Write Add. Decode	2M x 9 Array	2M x 9 Array
	Read Data Reg.
		18
		9
		9

Read Add. Decode

							9
	Output
		Logic
					R/W
	Control
				9					CQ
Reg.			Reg.					CQ
						9
				9				DQ[8:0]
Reg.
								QVLD

Document Number: 001-06347 Rev. *D Page 2 of 27

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