Cypress CY7C1266V18, CY7C1268V18, CY7C1270V18, CY7C1277V18 - page 24

CY7C1266V18, CY7C1277V18

CY7C1268V18, CY7C1270V18

Document Number: 001-06347 Rev. *D Page 24 of 27

Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit

www.cypress.com for actual products offered.

Speed

(MHz) Ordering Code Package

Diagram Package Type Operating

Range

400 CY7C1266V18-400BZC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Commercial

CY7C1277V18-400BZC

CY7C1268V18-400BZC

CY7C1270V18-400BZC

CY7C1266V18-400BZXC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

CY7C1277V18-400BZXC

CY7C1268V18-400BZXC

CY7C1270V18-400BZXC

CY7C1266V18-400BZI 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Industrial

CY7C1277V18-400BZI

CY7C1268V18-400BZI

CY7C1270V18-400BZI

CY7C1266V18-400BZXI 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

CY7C1277V18-400BZXI

CY7C1268V18-400BZXI

CY7C1270V18-400BZXI

375 CY7C1266V18-375BZC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Commercial

CY7C1277V18-375BZC

CY7C1268V18-375BZC

CY7C1270V18-375BZC

CY7C1266V18-375BZXC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

CY7C1277V18-375BZXC

CY7C1268V18-375BZXC

CY7C1270V18-375BZXC

CY7C1266V18-375BZI 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Industrial

CY7C1277V18-375BZI

CY7C1268V18-375BZI

CY7C1270V18-375BZI

CY7C1266V18-375BZXI 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

CY7C1277V18-375BZXI

CY7C1268V18-375BZXI

CY7C1270V18-375BZXI

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Contents

Main CY7C1266V18, CY7C1277V18 CY7C1268V18, CY7C1270V18 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations Functional Description Selection Guide CY7C1266V18, CY7C1277V18 CY7C1268V18, CY7C1270V18 Document Number: 001-06347 Rev. *D Page 2 of 27 Logic Block Diagram (CY7C1266V18) Logic Block Diagram (CY7C1277V18) 2M x 8 Array 2M x 8 Array Logic Block Diagram (CY7C1268V18) Logic Block Diagram (CY7C1270V18) 1M x 18 Array 1M x 18 Array 512K x 36 Array 512K x 36 Array Pin Configurations CY7C1266V18 (4M x 8) 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1277V18 (4M x 9) Pin Configurations CY7C1268V18 (2M x 18) 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1270V18 (1M x 36) CY7C1266V18, CY7C1277V18 CY7C1268V18, CY7C1270V18 Pin Definitions CY7C1266V18, CY7C1277V18 CY7C1268V18, CY7C1270V18 Pin Definitions CY7C1266V18, CY7C1277V18 CY7C1268V18, CY7C1270V18 Functional Overview Read Operations Write Operations Byte Write Operations Application Example Truth Table BUS MASTER (CPU or ASIC) SRAM#1 SRAM#2 Page Page CY7C1266V18, CY7C1277V18 CY7C1268V18, CY7C1270V18 IEEE 1149.1 Serial Boundary Scan (JTAG) Disabling the JTAG Feature Test Access Port Test Clock Test Mode Select Page TAP Controller State Diagram TAP Controller Block Diagram TAP Controller TAP Electrical Characteristics TAP AC Switching Characteristics TAP Timing and Test Conditions Test Clock Test Mode Select TCK TMS Test Data In TDI Test Data Out TDO Identification Register Definitions Scan Register Sizes Instruction Codes CY7C1266V18, CY7C1277V18 CY7C1268V18, CY7C1270V18 Boundary Scan Order Power Up Sequence in DDR-II+ SRAM Power Up Sequence Clock Start (Clock Starts after VDD/VDDQ is Stable) Fix HIGH (tie to VDDQ) DLL Constraints Maximum Ratings Operating Range Electrical Characteristics DC Electrical Characteristics AC Input Requirements Capacitance Thermal Resistance AC Test Loads and Waveforms Switching Characteristics Document Number: 001-06347 Rev. *D Page 23 of 27 Switching Waveforms Read/Write/Deselect Sequence READ READ 12345678910 Figure 5. Waveform for 2.5 Cycle Read Latency Page Ordering Information CY7C1266V18, CY7C1277V18 CY7C1268V18, CY7C1270V18 Document Number: 001-06347 Rev. *D Page 26 of 27 [+] Feedback [+] Feedback Package Diagram Figure 6. 165-ball FBGA (15 x 17 x 1.40 mm), 51-85195 CY7C1266V18, CY7C1277V18 CY7C1268V18, CY7C1270V18 Document History Page