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Cypress CY7C1297H manual Timing Diagrams continued, ZZ Mode Timing20, Page 13 of, + Feedback

Models: CY7C1297H

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CY7C1297H

Timing Diagrams (continued)

ZZMode Timing[20, 21]

CLK

t ZZ

t ZZI

ISUPPLY

I DDZZ

ALL INPUTS (except ZZ)

Outputs (Q)

High-Z

DON’T CARE

t ZZREC

t RZZI

DESELECT or READ Only

Notes:

20.Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.

21.DQs are in High-Z when exiting ZZ sleep mode.

Document #: 38-05669 Rev. *B

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Contents

Logic Block Diagram FeaturesCY7C1297H Functional Description1Selection Guide Pin Configuration 100-Pin TQFP15CY7C1297H CY7C1297HPower supply inputs to the core of the device Pin DescriptionsPower supply for the I/O circuitry CY7C1297HLinear Burst Address Table MODE = GND Interleaved Burst Address Table MODE = Floating or VDDFunctional Overview CY7C1297HCY7C1297H ZZ Mode Electrical CharacteristicsCY7C1297H Truth Table for Read/Write2Function BW BOperating Range Maximum RatingsElectrical Characteristics Over the Operating Range 7 CY7C1297HThermal Resistance9 Capacitance9AC Test Loads and Waveforms CY7C1297HCY7C1297H Switching Characteristics Over the Operating Range 10CY7C1297H Timing DiagramsRead Cycle Timing16 + FeedbackCY7C1297H Timing Diagrams continuedWrite Cycle Timing16 + FeedbackCY7C1297H Timing Diagrams continuedRead/Write Timing16, 18 + FeedbackZZ Mode Timing20 Timing Diagrams continuedCY7C1297H Page 13 ofOrdering Information Package DiagramCY7C1297H Issue Date Document HistoryCY7C1297H Document Title CY7C1297H 1-Mbit 64K x 18 Flow-Through Sync SRAM