Cypress CY7C1297H manual Pin Descriptions, Name, Power supply inputs to the core of the device

										CY7C1297H
	Pin Descriptions
				Name			I/O	Description
		A0, A1, A					Input-	Address Inputs used to select one of the 64K address locations. Sampled at the rising edge
							Synchronous	of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0]
								feed the 2-bit counter.
				A,		B	Input-	Byte Write Select Inputs, active LOW. Qualified with		to conduct Byte Writes to the SRAM.
		BW			BW				BWE
							Synchronous	Sampled on the rising edge of CLK.
							Input-	Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global
		GW
							Synchronous	Write is conducted (ALL bytes are written, regardless of the values on BW[A:B] and BWE).
							Input-	Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be
		BWE
							Synchronous	asserted LOW to conduct a Byte Write.
		CLK					Input-	Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the
							Clock	burst counter when ADV is asserted LOW, during a burst operation.
			1				Input-	Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
		CE
							Synchronous	CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only
								when a new external address is loaded.
		CE2					Input-	Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
							Synchronous	CE1 and CE3 to select/deselect the device. CE2 is sampled only when a new external address is
								loaded.
			3				Input-	Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
		CE
							Synchronous	CE1 and CE2 to select/deselect the device. CE3 is sampled only when a new external address is
								loaded.
							Input-	Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When
		OE
							Asynchronous	LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as
								input data pins. OE is masked during the first clock of a Read cycle when emerging from a
								deselected state.
							Input-	Advance Input signal, sampled on the rising edge of CLK. When asserted, it automatically
		ADV
							Synchronous	increments the address in a burst cycle.
							Input-	Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When
		ADSP
							Synchronous	asserted LOW, addresses presented to the device are captured in the address registers. A[1:0]
								are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is
								recognized. ASDP is ignored when CE1 is deasserted HIGH
							Input-	Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When
		ADSC
							Synchronous	asserted LOW, addresses presented to the device are captured in the address registers. A[1:0]
								are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is
								recognized.
		ZZ					Input-	ZZ “Sleep” Input, active HIGH. When asserted HIGH places the device in a non-time-critical
							Asynchronous	“sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or
								left floating. ZZ pin has an internal pull-down.
		DQs					I/O-	Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered
		DQPA, DQPB					Synchronous	by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
								specified by the addresses presented during the previous clock rise of the Read cycle. The
								direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs.
								When HIGH, DQs and DQP[A:B] are placed in a tri-state condition.
		VDD					Power Supply	Power supply inputs to the core of the device.
		VSS					Ground	Ground for the device.
		VDDQ					I/O Power	Power supply for the I/O circuitry.
							Supply
		MODE					Input-	Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left
							Static	floating selects interleaved burst sequence. This is a strap pin and should remain static during
								device operation. Mode Pin has an internal pull-up.
		NC						No Connects. Not Internally connected to the die. 2M, 4M, 9M, 18M, 72M, 144M, 288M, 576M
								and 1G are address expansion pins and are not internally connected to the die.
Document #: 38-05669 Rev. *B										Page 3 of 15

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