CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18

TAP Controller Block Diagram

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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Bypass Register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TDI

 

 

 

 

 

Selection

 

 

 

 

 

 

 

 

 

2

1

0

 

 

 

 

Selection

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Instruction Register

 

 

 

 

 

 

 

 

 

 

 

 

 

Circuitry

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Circuitry

 

 

 

 

 

 

31

 

30

29

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2

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Identification Register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

106

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Boundary Scan Register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TCK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TAP Controller

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TMS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TDO

TAP Electrical Characteristics

Over the Operating Range [10, 11, 12]

Parameter

Description

Test Conditions

Min

Max

Unit

VOH1

Output HIGH Voltage

IOH = 2.0 mA

1.4

 

V

VOH2

Output HIGH Voltage

IOH = 100 μA

1.6

 

V

VOL1

Output LOW Voltage

IOL = 2.0 mA

 

0.4

V

VOL2

Output LOW Voltage

IOL = 100 μA

 

0.2

V

VIH

Input HIGH Voltage

 

0.65VDD

VDD + 0.3

V

VIL

Input LOW Voltage

 

–0.3

0.35VDD

V

IX

Input and Output Load Current

GND VI VDD

–5

5

μA

Notes

10.These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table.

11.Overshoot: VIH(AC) < VDDQ + 0.85V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > 1.5V (Pulse width less than tCYC/2).

12.All Voltage referenced to Ground.

Document Number: 001-07161 Rev. *D

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Cypress CY7C1321CV18, CY7C1319CV18, CY7C1317CV18, CY7C1917CV18 TAP Controller Block Diagram, TAP Electrical Characteristics

CY7C1321CV18, CY7C1917CV18, CY7C1319CV18, CY7C1317CV18 specifications

Cypress Semiconductor Corporation, a leading provider of advanced embedded memory solutions, offers a series of high-performance SRAM (Static Random Access Memory) devices ideal for a variety of applications. Among these devices are the CY7C1317CV18, CY7C1319CV18, CY7C1917CV18, and CY7C1321CV18. These components are designed to meet the growing demands for non-volatile memory in consumer electronics, automotive systems, telecommunications, and industrial applications.

The CY7C1317CV18 and CY7C1319CV18 are both 256K-bit static RAMs with distinct features. The CY7C1317CV18 offers a dual-port architecture, enabling concurrent access from multiple sources, which substantially enhances performance in data-intensive applications. On the other hand, the CY7C1319CV18 is designed for single-port access, making it ideal for simpler applications that do not require simultaneous data reads and writes.

Further extending Cypress's SRAM portfolio, the CY7C1917CV18 provides a 2M-bit memory configuration with fast access times, high-density storage, and low power consumption. It is particularly well-suited for applications needing quick data retrieval while maintaining efficiency. The architecture of the CY7C1917CV18 allows it to be integrated seamlessly into systems requiring reliable and robust data storage.

Completing the lineup is the CY7C1321CV18, which features an innovative 1M-bit SRAM design. This SRAM is known for its low latency and high speed, making it an excellent choice for high-performance computing applications. It supports a wide operating voltage range and provides a reliable solution for volatile memory needs, especially in fast caching scenarios.

These SRAM devices utilize advanced CMOS technology to achieve high speed and low power characteristics, making them competitive choices in the market. Their robust performance ensures that they satisfy the stringent requirements of various applications, including high-speed networking, graphics processing, and instrumentation.

In terms of reliability, all four devices are built to endure challenging operating conditions and provide excellent data retention. They are offered in compact packages that facilitate easy integration into PCBs, optimizing space and enhancing design flexibility. The combination of performance, low power consumption, and scalability makes Cypress's SRAM products particularly advantageous for next-generation applications across multiple industries.