Cypress CY7C1317CV18, CY7C1319CV18, CY7C1321CV18, CY7C1917CV18 CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18

CY7C1317CV18, CY7C1917CV18
CY7C1319CV18, CY7C1321CV18
Document Number: 001-07161 Rev. *D Page 3 of 31
Logic Block Diagram (CY7C1319CV18)
Logic Block Diagram (CY7C1321CV18)
Write
Reg
CLK
A(19:0)
Gen.
K
K
Control
Logic
Address
Register
Read Add. Decode
Read Data Reg.
R/W
Output
Logic
Reg.
Reg.
Reg.
36
72
18
BWS[1:0]
VREF
Write Add. Decode
36
20
C
C
18
LD
Control
R/W
DOFF
256K x 18 Array 256K x 18 Array
18
Write
Reg Write
Reg Write
Reg
256K x 18 Array 256K x 18 Array
18
18
Burst
Logic
2
A(1:0)
18
A(19:2)
DQ[17:0]
18
CQ
CQ
Write
Reg
CLK
A(18:0)
Gen.
K
K
Control
Logic
Address
Register
Read Add. Decode
Read Data Reg.
R/W
Output
Logic
Reg.
Reg.
Reg.
72
144
36
BWS[3:0]
VREF
Write Add. Decode
72
19
C
C
36
LD
Control
R/W
DOFF
128K x 36 Array 128K x 36 Array
36
Write
Reg Write
Reg Write
Reg
128K x 36 Array 128K x 36 Array
36
36
Burst
Logic
2
A(1:0)
17
A(18:2)
DQ[35:0]
36
CQ
CQ
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