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Cypress CY7C1317CV18, CY7C1319CV18, CY7C1321CV18, CY7C1917CV18 Switching Waveforms

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CY7C1317CV18, CY7C1917CV18

CY7C1319CV18, CY7C1321CV18

Document Number: 001-07161 Rev. *D Page 26 of 31

Switching Waveforms

Figure 5. Read/Write/Deselect Sequence [27, 28, 29]

12345678910 11 12 13

READ

(burst of 4)

READ

(burst of 4)

READ

(burst of 4)

NOP NOP WRITE

(burst of 4)

WRITE

(burst of 4)

NOP

DON’T CARE UNDEFINED

R/W

tKH tKL tCYC tKHKH

tSCtHC

tSA tHA

A0 A1 A2 A3 A4

Q00 Q01 Q02 Q03 Q10 Q11 Q12 Q13 D20 D21 D22 D23 D30 D31 D32 D33

tHD

tSD

tHD

tSD

tKHCH

tCLZ

tDOH

tCO

tCQD

tCQDOH

tCHZ

tCCQO

tKH tKL tCYC tKHKH

tCQOH

tCCQO

tCQOH

tCQHCQH

tCQH

Q40

Notes

27.Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0 + 1.

28.Outputs are disabled (High-Z) one clock cycle after a NOP.

29.In this example, if address A4 = A3, then data Q40 = D30, Q41 = D31, Q42 = D32, and Q43 = D43. Write data is forwarded immediately as read results. This note

applies to the whole diagram.

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Contents

Main 18-Mbit DDR-II SRAM 4-Word Burst Architecture CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Features Configurations Functional Description CY7C1319CV18, CY7C1321CV18 Logic Block Diagram (CY7C1317CV18) Logic Block Diagram (CY7C1917CV18) CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev. *D Page 3 of 31 Logic Block Diagram (CY7C1319CV18) Logic Block Diagram (CY7C1321CV18) Pin Configuration 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout Pin Configuration 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout Pin Definitions CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Pin Definitions CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Functional Overview Read Operations Write Operations Byte Write Operations CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Depth Expansion Programmable Impedance Echo Clocks DLL Application Example Truth Table SRAM#1 SRAM#2 BUS MASTER (CPU or ASIC) Burst Address Table Page CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 IEEE 1149.1 Serial Boundary Scan (JTAG) Disabling the JTAG Feature Test Access PortTest Clock Test Mode Select (TMS) Page TAP Controller State Diagram TAP Controller Block Diagram TAP Electrical Characteristics CY7C1317CV18, CY7C1917CV18 TAP AC Switching Characteristics TAP Timing and Test Conditions CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Identification Register Definitions Scan Register Sizes Instruction Codes CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Boundary Scan Order Power Up Sequence in DDR-II SRAM VV Power Up Sequence DLL Constraints / CY7C1319CV18, CY7C1321CV18 Maximum Ratings Operating Range Electrical Characteristics DC Electrical Characteristics Electrical Characteristics DC Electrical Characteristics Capacitance Thermal Resistance Page Switching Characteristics Switching Waveforms Figure 5. Read/Write/Deselect Sequence Page Page Ordering Information Package Diagram Figure 6. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180 [+] Feedback SOLDERPAD TYPE : NON-SOLDER MASK DEFINED (NSMD) 1.40MAX. CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC Solutions