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Cypress CY7C1317CV18, CY7C1319CV18, CY7C1321CV18, CY7C1917CV18 Ordering Information

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CY7C1317CV18, CY7C1917CV18

CY7C1319CV18, CY7C1321CV18

Document Number: 001-07161 Rev. *D Page 29 of 31

167 CY7C1317CV18-167BZC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial

CY7C1917CV18-167BZC

CY7C1319CV18-167BZC

CY7C1321CV18-167BZC

CY7C1317CV18-167BZXC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1917CV18-167BZXC

CY7C1319CV18-167BZXC

CY7C1321CV18-167BZXC

CY7C1317CV18-167BZI 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Industrial

CY7C1917CV18-167BZI

CY7C1319CV18-167BZI

CY7C1321CV18-167BZI

CY7C1317CV18-167BZXI 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1917CV18-167BZXI

CY7C1319CV18-167BZXI

CY7C1321CV18-167BZXI

Ordering Information (continued)

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

visit www.cypress.com for actual products offered.

Speed

(MHz) Ordering Code Package

Diagram Package Type Operating

Range

[+] Feedback

Contents

Main 18-Mbit DDR-II SRAM 4-Word Burst Architecture CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Features Configurations Functional Description CY7C1319CV18, CY7C1321CV18 Logic Block Diagram (CY7C1317CV18) Logic Block Diagram (CY7C1917CV18) CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev. *D Page 3 of 31 Logic Block Diagram (CY7C1319CV18) Logic Block Diagram (CY7C1321CV18) Pin Configuration 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout Pin Configuration 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout Pin Definitions CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Pin Definitions CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Functional Overview Read Operations Write Operations Byte Write Operations CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Depth Expansion Programmable Impedance Echo Clocks DLL Application Example Truth Table SRAM#1 SRAM#2 BUS MASTER (CPU or ASIC) Burst Address Table Page CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 IEEE 1149.1 Serial Boundary Scan (JTAG) Disabling the JTAG Feature Test Access PortTest Clock Test Mode Select (TMS) Page TAP Controller State Diagram TAP Controller Block Diagram TAP Electrical Characteristics CY7C1317CV18, CY7C1917CV18 TAP AC Switching Characteristics TAP Timing and Test Conditions CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Identification Register Definitions Scan Register Sizes Instruction Codes CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Boundary Scan Order Power Up Sequence in DDR-II SRAM VV Power Up Sequence DLL Constraints / CY7C1319CV18, CY7C1321CV18 Maximum Ratings Operating Range Electrical Characteristics DC Electrical Characteristics Electrical Characteristics DC Electrical Characteristics Capacitance Thermal Resistance Page Switching Characteristics Switching Waveforms Figure 5. Read/Write/Deselect Sequence Page Page Ordering Information Package Diagram Figure 6. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180 [+] Feedback SOLDERPAD TYPE : NON-SOLDER MASK DEFINED (NSMD) 1.40MAX. CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC Solutions