Cypress CY7C1354CV25, CY7C1356CV25 Ordering Information

CY7C1354CV25

CY7C1356CV25

Document #: 38-05537 Rev. *H Page 24 of 28

250 CY7C1354CV25-250AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial

CY7C1356CV25-250AXC

CY7C1354CV25-250BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1356CV25-250BGC

CY7C1354CV25-250BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

CY7C1356CV25-250BGXC

CY7C1354CV25-250BZC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

CY7C1356CV25-250BZC

CY7C1354CV25-250BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free

CY7C1356CV25-250BZXC

CY7C1354CV25-250AXI 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Industrial

CY7C1356CV25-250AXI

CY7C1354CV25-250BGI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1356CV25-250BGI

CY7C1354CV25-250BGXI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

CY7C1356CV25-250BGXI

CY7C1354CV25-250BZI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

CY7C1356CV25-250BZI

CY7C1354CV25-250BZXI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free

CY7C1356CV25-250BZXI

Ordering Information (continued)

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

visit www.cypress.com for actual products offered.

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Contents

Main 9-Mbit (256K x 36/512K x 18) Pi elined SRAM with NoBL Architecture p CY7C1354CV25 CY7C1356CV25 Features CY7C1354CV25 CY7C1356CV25 Document #: 38-05537 Rev. *H Page 2 of 28 A0, A1, A C C ADV/LD CY7C1354CV25 CY7C1356CV25 Document #: 38-05537 Rev. *H Page 3 of 28 Pin Configurations (256K 36) (512K 18) MODE CY7C1354CV25 Pin Configurations 2345671 A B C D E F G H J K L M N P R T U CY7C1354CV25 (256K 36) 119-Ball BGA Pinout CY7C1354CV25 CY7C1356CV25 Pin Configurations CY7C1354CV25 (256K 36) CY7C1356CV25 (512K 18) 2345671 A B C D E F G H J K L M N P R CY7C1356CV25 Pin Definitions CY7C1354CV25 CY7C1356CV25 Functional Overview Pin Definitions Interleaved Burst Address Table (MODE = Floating or VDD) Linear Burst Address Table (MODE = GND) ZZ Mode Electrical Characteristics Truth Table Partial Write Cycle Description Truth Table IEEE 1149.1 Serial Boundary Scan (JTAG) TAP Controller State Diagram TAP Controller Block Diagram Page TAP Ti ming TAP AC Switching Characteristics CY7C1354CV25 CY7C1356CV25 2.5V TAP AC Test Conditions F DO T Boundary Scan Exit Order (256K 36) Boundary Scan Exit Order (512K 18) Maximum Ratings Operating Range Electrical Characteristics Capacitance Thermal Resistance AC Test Loads and Waveforms Switching Characteristics Switching Waveforms Read/Write Timing OE Out (DQ) n- Page ZZ Mode Timing Ordering Information Page Ordering Information CY7C1354CV25 CY7C1356CV25 Package Diagrams A 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) (51-85050) Package Diagrams 0.900.05 51-85115-*B 0.56 119-Ball BGA (14 x 22 x 2.4 mm) (51-85115) Package Diagrams 1.40 MAX. 51-85180-*A - SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD) Document History Page