CY7C1471V33CY7C1473V33CY7C1475V33

Document #: 38-05288 Rev. *J Page 3 of 32

Logic Block Diagram – CY7C1475V33 (1M x 72)

A0, A1, A
C
MODE
CE1
CE2
CE3
OE
READ LOGIC
DQs
DQPa
DQPb
DQPc
DQPd
DQPe
DQPf
DQPg
DQPh
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
MEMORY
ARRAY
E
E
INPUT
REGISTER 0
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
BURST
LOGIC
A0'
A1'
D1
D0
Q1
Q0
A0
A1
C
ADV/LD
ADV/LD
E
INPUT
REGISTER 1
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
CLK
CEN
WRITE
DRIVERS
BW
a
BW
b
WE
ZZ
BW
c
BW
d
BW
e
BW
f
BW
g
BW
h
Sleep Control
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
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