Cypress CY7C1473V33 manual Ieee 1149.1 Serial Boundary Scan Jtag, TAP Controller State Diagram

CY7C1471V33

CY7C1473V33

CY7C1475V33

IEEE 1149.1 Serial Boundary Scan (JTAG)

The CY7C1471V33, CY7C1473V33, and CY7C1475V33 incorporate a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM. Note that the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC-standard 3.3V or 2.5V IO logic levels.

Test Access Port (TAP)

Test Clock (TCK)

The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK.

Test MODE SELECT (TMS)

The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level.

The CY7C1471V33, CY7C1473V33, and CY7C1475V33 contain a TAP controller, instruction register, boundary scan register, bypass register, and ID register.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are inter- nally pulled up and may be unconnected. They may alternately be connected to VDD through a pull up resistor. TDO must be left unconnected. During power up, the device comes up in a reset state, which does not interfere with the operation of the device.

TAP Controller State Diagram

Test Data-In (TDI)

The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information about loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See TAP Controller Block Diagram.)

Test Data-Out (TDO)

The TDO output ball is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine. The output changes on the falling edge of TCK. TDO is connected to the least significant

1 TEST-LOGIC RESET

0

0 RUN-TEST/ 1

IDLE

SELECT	1	SELECT	1
DR-SCA N		IR-SCA N
0		0

bit (LSB) of any register. (See TAP Controller State Diagram.)

TAP Controller Block Diagram

1	CA PTURE-DR		1	CA PTURE-IR
0			0
	SHIFT-DR	0		SHIFT-IR	0
1			1
		1			1
	EXIT1-DR			EXIT1-IR
0			0
	PA USE-DR	0		PA USE-IR	0
1			1
0			0
	EXIT2-DR			EXIT2-IR
1			1
	UPDA TE-DR			UPDA TE-IR

TDI

Selection Circuitry

									0
			Bypass Register
							2	1	0	Selection
	Instruction Register
										Circuitry
	31	30	29	.	.	.	2	1	0
Identification Register
	x	.	.	.	.	.	2	1	0
Boundary Scan Register

TDO

1 0 1 0

TCK

TAP CONTROLLER

TM S

The 0/1 next to each state represents the value of TMS at the rising edge of TCK.

Performing a TAP Reset

A RESET is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating.

During power up, the TAP is reset internally to ensure that TDO comes up in a High-Z state.

Document #: 38-05288 Rev. *J Page 13 of 32

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