CY7C1471V33

CY7C1473V33

CY7C1475V33

Document Title: CY7C1471V33/CY7C1473V33/CY7C1475V33, 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL™ Architecture

Document Number: 38-05288

REV.

ECN NO.

Issue

Orig. of Change

Description of Change

Date

 

 

 

 

 

 

 

 

 

*I

472335

See ECN

VKN

Corrected the typo in the pin configuration for 209-Ball FBGA pinout

 

 

 

 

(Corrected the ball name for H9 to VSS from VSSQ).

 

 

 

 

Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND.

 

 

 

 

Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC

 

 

 

 

Switching Characteristics table.

 

 

 

 

Updated the Ordering Information table.

*J

1274732

See ECN

VKN/AESA

Corrected typo in the “NOP, STALL and DESELECT Cycles” waveform

 

 

 

 

 

Document #: 38-05288 Rev. *J

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Cypress CY7C1471V33, CY7C1475V33, CY7C1473V33 manual Vkn/Aesa