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Cypress CY7C1471V33, CY7C1473V33, CY7C1475V33 123456789 CLK, 10, DONT CARE UNDEFINED, OE, BW, CEN, WE, CE, ADV/LD, ADDRESS A1 A2 A3 A4 A5 A6 A7, DQ COMMAND

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CY7C1471V33

CY7C1473V33

CY7C1475V33

Document #: 38-05288 Rev. *J Page 24 of 32

Switching Waveforms

Figure1 shows re ad-write timing waveform.[20, 21, 22]

Figure 1. Read/Write Timing

WRITE

D(A1)

123456789CLK

tCYC

tCL

tCH

10CE

tCEH

tCES

WECEN

tCENH

tCENS

BWX

ADV/LD

tAH

tAS

ADDRESS A1 A2 A3 A4 A5 A6 A7

tDH

tDS

DQCOMMAND

tCLZ

D(A1) D(A2) Q(A4)Q(A3)

D(A2+1)

tDOH tCHZ

tCDV

WRITE

D(A2)

BURST

WRITE

D(A2+1)

READ

Q(A3)

READ

Q(A4)

BURST

READ

Q(A4+1)

WRITE

D(A5)

READ

Q(A6)

WRITE

D(A7)

DESELECT

tOEV

tOELZ

tOEHZ

DON’T CARE UNDEFINED

D(A5)

tDOH

Q(A4+1)

D(A7)Q(A6)

Notes

20.For this waveform ZZ is tied LOW.

21.When CE is LOW, CE1 is LOW, CE2 is HIGH, and CE3 is LOW. When CE is HIGH, CE1 is HIGH, CE2 is LOW or CE3 is HIGH.

22.Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.

[+] Feedback

Contents

Main 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture CY7C1471V33 CY7C1473V33 CY7C1475V33 Features Functional Description Selection Guide Logic Block Diagram CY7C1471V33 (2M x 36) C B DQP Logic Block Diagram CY7C1473V33 (4M x 18) CY7C1471V33 CY7C1473V33 CY7C1475V33 Document #: 38-05288 Rev. *J Page 3 of 32 Logic Block Diagram CY7C1475V33 (1M x 72) DQs DQPa DQPb DQPc DQPd DQPe DQPf DQPg DQPh CY7C1471V33 CY7C1473V33 CY7C1475V33 Pin Configurations 100-Pin TQFP Pinout CY7C1471V33 CY7C1475V33 Document #: 38-05288 Rev. *J Page 5 of 32 100-Pin TQFP Pinout CY7C1473V33 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1471V33 (2M x 36) CY7C1473V33 (4M x 18) 2345671 A B C D E F G H J K L M N P R 891011 2345671 A B C D E F G H J K L M N P R CY7C1471V33 CY7C1473V33 CY7C1475V33 CY7C1475V33 (1M 72) A B C D E F G H J K L M N P R T U V W 123456789 1110 209-Ball FBGA (14 x 22 x 1.76 mm) Pinout Pin Definitions Functional Overview Pin Definitions Interleaved Burst Address Table (MODE = Floating or VDD) Linear Burst Address Table (MODE = GND) ZZ Mode Electrical Characteristics Truth Table Page IEEE 1149.1 Serial Boundary Scan (JTAG) TAP Controller State Diagram TAP Controller Block Diagram CY7C1471V33 CY7C1473V33 CY7C1475V33 TAP Ti ming TAP AC Switching Characteristics 3.3V TAP AC Test Conditions 2.5V TAP AC Test Conditions 50 TDO 50 Identification Register Definitions Scan Register Sizes Identification Codes Boundary Scan Exit Order (2M x 36) Boundary Scan Exit Order (4M x 18) Boundary Scan Exit Order (1M x 72) Maximum Ratings Operating Range Electrical Characteristics Capacitance Thermal Resistance AC Test Loads and Waveforms Switching Characteristics Switching Waveforms Figure1 shows re ad-write timing waveform.[20, 21, 22] Figure 1. Read/Write Timing 123456789 CLK 10 DONT CARE UNDEFINED OE BW Page Figure3 shows ZZ Mode timing waveform.[24, 25] Figure 3. ZZ Mode Timing Switching Waveforms Ordering Information Document #: 38-05288 Rev. *J Page 28 of 32 Package Diagrams Figure 4. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm), 51-85050 A Figure 5. 165-Ball FBGA (15 x 17 x 1.4 mm), 51-85165 Package Diagrams 51-85165-*A Page Document History Page