Manuals / Brands / Computer Equipment / Computer Hardware / Cypress / Computer Equipment / Computer Hardware

Cypress CY7C1516JV18, CY7C1518JV18, CY7C1520JV18, CY7C1527JV18 Switching Waveforms

1 26

Download 26 pages, 661.29 Kb

CY7C1516JV18, CY7C1527JV18

CY7C1518JV18, CY7C1520JV18

Document Number: 001-12559 Rev. *D Page 23 of 26

Switching Waveforms

Figure 5. Read/Write/Deselect Sequence [26, 27, 28]

READ READREAD NOP NOP WRITEWRITE

NOP

12345678910

Q40

tKHCH

tCO

ttHC

ttHA

tSD

tHD

tKHCH

tSD

tHD

DON’T CARE UNDEFINED

tCLZ tDOH tCHZ

tKH tKHKH

tKL tCYC

D20 D21 D30 D31

Q00 Q11Q01 Q10

A1 A2 A3 A4

Q41

tCCQO

tCQOH

tCCQO

tCQOH

tKL tCYC

R/W

CQ#

tKH tKHKH

tCQD

tCQDOH

tCQH tCQHCQH

Notes

26.Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0 + 1.

27.Outputs are disabled (High-Z) one clock cycle after a NOP.

28.In this example, if address A2 = A1, then data D20 = Q10 and D21 = Q11. Write data is forwarded immediately as read results. This note applies to the whole diagram.

[+] Feedback

Contents

Main 72-Mbit DDR-II SRAM 2-Word Burst Architecture CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Features Configurations Functional Description CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Document Number: 001-12559 Rev. *D Page 2 of 26 Logic Block Diagram (CY7C1516JV18) Logic Block Diagram (CY7C1527JV18) 4M x 8 Array 4M x 8 Array Logic Block Diagram (CY7C1518JV18) Logic Block Diagram (CY7C1520JV18) 2M x 18 Array 2M x 18 Array 1M x 36 Array 1M x 36 Array Pin Configuration 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Pin Configuration 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1516JV18, CY7C1527JV18 Pin Definitions CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Pin Definitions CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Functional Overview Single Clock Mode DDR Operation Application Example SRAM#1 SRAM#2 BUS MASTER (CPU or ASIC) Truth Table Burst Address Table Page IEEE 1149.1 Serial Boundary Scan (JTAG) Disabling the JTAG Feature Test Access PortTest Clock Test Mode Select (TMS) Test D ata- In (T DI) Page TAP Controller State Diagram CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 TAP Controller Block Diagram TAP Electrical Characteristics CY7C1516JV18, CY7C1527JV18 TAP AC Switching Characteristics TAP Timing and Test Conditions Identification Register Definitions Scan Register Sizes Instruction Codes CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Boundary Scan Order Power Up Sequence in DDR-II SRAM VV Power Up Sequence DLL Constraints / CY7C1518JV18, CY7C1520JV18 Maximum Ratings Operating Range Electrical Characteristics DC Electrical Characteristics Capacitance Thermal Resistance Switching Characteristics Document Number: 001-12559 Rev. *D Page 23 of 26 Switching Waveforms Figure 5. Read/Write/Deselect Sequence READ READREAD NOP NOP WRITEWRITE NOP 12345678910 Ordering Information Document Number: 001-12559 Rev. *D Page 25 of 26 Package Diagram [+] Feedback Figure 6. 165-Ball FBGA (15 x 17 x 1.40 mm), 51-85195 51-85195-*A Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC Solutions Document History Page