Cypress CY7C1516JV18 Logic Block Diagram CY7C1518JV18, Logic Block Diagram CY7C1520JV18, Bws

CY7C1516JV18, CY7C1527JV18

CY7C1518JV18, CY7C1520JV18

Logic Block Diagram (CY7C1518JV18)

			A0			Burst
						Logic
	22				21
A(21:0)				A(21:1)		Address
						Register
		LD

K

CLK

K Gen.

DOFF

VREF
		Control
R/W
		Logic
BWS
	[1:0]

	Write	Write
Decode	Reg	Reg	Decode
	2M x	2M x			18
WriteAdd.	18Array	18Array	ReadAdd.	Logic
				Output	R/W
	Read Data Reg.			Control	C
					C

36
18				18		CQ
		Reg.	Reg.			CQ
	18	Reg.		18	18	DQ[17:0]

Logic Block Diagram (CY7C1520JV18)

			A0			Burst
						Logic
	21				20
A(20:0)				A(20:1)		Address
						Register
		LD

K

CLK

K Gen.

DOFF

VREF
		Control
R/W
		Logic
BWS
	[3:0]

	Write	Write
DecodeAdd.Write	Reg	Reg	DecodeAdd.Read
	1Mx36Array	1Mx36Array		Logic	36
				Output	R/W
	Read Data Reg.			Control	C
					C

72
36		Reg.	Reg.	36		CQ
						CQ
	36	Reg.		36	36	DQ[35:0]

Document Number: 001-12559 Rev. *D Page 3 of 26

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