Manuals / Cypress / Computer Equipment / Computer Hardware

Cypress CY7C1518JV18, CY7C1520JV18, CY7C1527JV18, CY7C1516JV18 manual Ordering Information

Models: CY7C1527JV18 CY7C1518JV18 CY7C1516JV18 CY7C1520JV18

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CY7C1516JV18, CY7C1527JV18

CY7C1518JV18, CY7C1520JV18

Ordering Information

Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered.

Speed	Ordering Code	Package	Package Type	Operating
(MHz)	Ordering Code	Diagram	Package Type	Range
300	CY7C1516JV18-300BZC	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)	Commercial

	CY7C1527JV18-300BZC

	CY7C1518JV18-300BZC

	CY7C1520JV18-300BZC

	CY7C1516JV18-300BZXC	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

	CY7C1527JV18-300BZXC

	CY7C1518JV18-300BZXC

	CY7C1520JV18-300BZXC

	CY7C1516JV18-300BZI	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)	Industrial

	CY7C1527JV18-300BZI

	CY7C1518JV18-300BZI

	CY7C1520JV18-300BZI

	CY7C1516JV18-300BZXI	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

	CY7C1527JV18-300BZXI

	CY7C1518JV18-300BZXI

	CY7C1520JV18-300BZXI

250	CY7C1516JV18-250BZC	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)	Commercial

	CY7C1527JV18-250BZC

	CY7C1518JV18-250BZC

	CY7C1520JV18-250BZC

	CY7C1516JV18-250BZXC	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

	CY7C1527JV18-250BZXC

	CY7C1518JV18-250BZXC

	CY7C1520JV18-250BZXC

	CY7C1516JV18-250BZI	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)	Industrial

	CY7C1527JV18-250BZI

	CY7C1518JV18-250BZI

	CY7C1520JV18-250BZI

	CY7C1516JV18-250BZXI	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

	CY7C1527JV18-250BZXI

	CY7C1518JV18-250BZXI

	CY7C1520JV18-250BZXI

Document Number: 001-12559 Rev. *D

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Cypress CY7C1518JV18, CY7C1520JV18, CY7C1527JV18, CY7C1516JV18 manual Ordering Information

Contents

Features ConfigurationsFunctional Description Selection Guide Logic Block Diagram CY7C1516JV18 Logic Block Diagram CY7C1527JV18Doff CLK Logic Block Diagram CY7C1518JV18 Logic Block Diagram CY7C1520JV18BWS Pin Configuration Ball Fbga 15 x 17 x 1.4 mm PinoutCY7C1516JV18 8M x CY7C1527JV18 8M x CY7C1518JV18 4M x CY7C1520JV18 2M x Pin Definitions Pin Name Pin Description Power Supply Inputs to the Core of the Device Power Supply Inputs for the Outputs of the DeviceTDO for Jtag TCK Pin for Jtag Single Clock Mode Functional OverviewDDR Operation Application Example Depth ExpansionProgrammable Impedance Echo Clocks Write Cycle Descriptions BWS0 BWS1NWS0 NWS1 BWS0 BWS0 BWS1 BWS2 BWS3 Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram State diagram for the TAP controller follows TAP Controller Block Diagram TAP Electrical CharacteristicsTDI TCK TAP AC Switching Characteristics TAP Timing and Test Conditions Identification Register Definitions Scan Register SizesInstruction Codes Boundary Scan Order Bit # Bump ID Power Up Sequence in DDR-II Sram Power Up SequenceDLL Constraints Electrical Characteristics DC Electrical CharacteristicsMaximum Ratings AC Electrical Characteristics CapacitanceThermal Resistance Parameter Description Test Conditions Max Unit Cypress Consortium Description 300 MHz 250 MHz Unit Parameter Min MaxDLL Timing Switching Waveforms NOPRead NOP Write Read Ordering Information Package Diagram Ball Fbga 15 x 17 x 1.40 mm Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC SolutionsREV ECN no Issue ORIG. Description of Change Date