CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18
Features
Configurations
Functional Description
CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18
Logic Block Diagram CY7C1541V18
Logic Block Diagram CY7C1556V18
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CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18
Logic Block Diagram CY7C1543V18
Logic Block Diagram CY7C1545V18
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Pin Configuration
165-Ball FBGA 15 x 17 x 1.4 mm Pinout
CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18
Pin Configuration continued
CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18
165-Ball FBGA 15 x 17 x 1.4 mm Pinout
CY7C1543V18, CY7C1545V18
CY7C1541V18, CY7C1556V18
Pin Definitions
CY7C1543V18, CY7C1545V18
Pin Definitions continued
CY7C1541V18, CY7C1556V18
Read Operations
CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18
Functional Overview
Write Operations
Depth Expansion
Valid Data Indicator QVLD
Application Example
Programmable Impedance
CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18
Truth Table
Write Cycle Descriptions
NWS0
CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18
Write Cycle Descriptions
Write Cycle Descriptions
Performing a TAP Reset
Disabling the JTAG Feature
Test Access Port-Test Clock
IEEE 1149.1 Serial Boundary Scan JTAG
BYPASS
SAMPLE Z
SAMPLE/PRELOAD
EXTEST
TAP Controller State Diagram
CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18
Page 14 of
TAP Controller Block Diagram
TAP Electrical Characteristics
CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18
TAP AC Switching Characteristics
TAP Timing and Test Conditions
CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18
Instruction Codes
Identification Register Definitions
Scan Register Sizes
CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18
Boundary Scan Order
CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18
DLL Constraints
Power Up Sequence in QDR-II+ SRAM
Power Up Sequence
K K VDD/VDDQ DOFF
Maximum Ratings
Electrical Characteristics
DC Electrical Characteristics
Operating Range
Capacitance
Electrical Characteristics continued
AC Electrical Characteristics
DC Electrical Characteristics
Thermal Resistance
CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18
Package
Switching Characteristics
CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18
Parameter
Q CQ CQ
Switching Waveforms
WPS A D QVLD
CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18
Ordering Information
CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18
Ordering Information continued
CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18
Figure 6. 165-ball FBGA 15 x 17 x 1.4 mm
Package Diagram
CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18
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CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18
Document History Page
ISSUE
Document Number