300 | Cypress CY7C1556V18, CY7C1543V18, CY7C1545V18, CY7C1541V18

CY7C1541V18, CY7C1556V18

CY7C1543V18, CY7C1545V18

Ordering Information (continued)

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered.

Speed	Ordering Code	Package	Package Type	Operating
(MHz)	Ordering Code	Diagram	Package Type	Range
300	CY7C1541V18-300BZC	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)	Commercial

	CY7C1556V18-300BZC

	CY7C1543V18-300BZC

	CY7C1545V18-300BZC

	CY7C1541V18-300BZXC	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

	CY7C1556V18-300BZXC

	CY7C1543V18-300BZXC

	CY7C1545V18-300BZXC

	CY7C1541V18-300BZI	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)	Industrial

	CY7C1556V18-300BZI

	CY7C1543V18-300BZI

	CY7C1545V18-300BZI

	CY7C1541V18-300BZXI	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

	CY7C1556V18-300BZXI

	CY7C1543V18-300BZXI

	CY7C1545V18-300BZXI

Document Number: 001-05389 Rev. *F

Page 26 of 28

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Cypress CY7C1556V18, CY7C1543V18, CY7C1545V18, CY7C1541V18 manual 300

Contents

Functional Description FeaturesConfigurations Selection Guide Doff Logic Block Diagram CY7C1541V18Logic Block Diagram CY7C1556V18 Logic Block Diagram CY7C1543V18 Logic Block Diagram CY7C1545V18 CY7C1541V18 8M x Pin ConfigurationBall Fbga 15 x 17 x 1.4 mm Pinout CY7C1556V18 8M x CY7C1545V18 4M x CY7C1543V18 4M xWPS BWS Negative Input Clock Input Pin DefinitionsPin Name Pin Description TDO for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TCK Pin for Jtag Write Operations Functional OverviewRead Operations Byte Write Operations Depth Expansion Valid Data Indicator QvldApplication Example Programmable Impedance Operation Truth TableWrite Cycle Descriptions Comments Device Write cycle description table for CY7C1556V18 followsWrite cycle description table for CY7C1545V18 follows Into the device. D359 remains unaltered Ieee 1149.1 Serial Boundary Scan Jtag Sample Z TAP Controller State Diagram State diagram for the TAP controller follows.12 TAP Controller Block Diagram TAP Electrical Characteristics TAP AC Switching Characteristics TAP Timing and Test Conditions Register Name Bit Size Identification Register DefinitionsScan Register Sizes Instruction Code Description Bit # Bump ID DLL Constraints Power Up Sequence in QDR-II+ SramPower Up Sequence Maximum Ratings Electrical CharacteristicsDC Electrical Characteristics Operating Range Parameter Description Test Conditions Max Unit AC Electrical CharacteristicsCapacitance Thermal Resistance Junction to Case Thermal ResistanceParameter Description Test Conditions Fbga Unit Parameter Min Max Switching CharacteristicsConsortium Description 375 MHz 333 MHz 300 MHz Unit High Switching Waveforms Read/Write/Deselect Sequence 31, 32 Ordering Information 300 Package Diagram Ball Fbga 15 x 17 x 1.4 mm NXR VEEIGS VKN/FSU