Cypress CY7C1541V18, CY7C1556V18 Logic Block Diagram CY7C1543V18, Logic Block Diagram CY7C1545V18

CY7C1541V18, CY7C1556V18

CY7C1543V18, CY7C1545V18

Logic Block Diagram (CY7C1543V18)

18

D[17:0]

20Address

A(19:0) Register

K

K CLK

Gen.

DOFF

VREF
		Control
WPS
		Logic
BWS
	[1:0]

Write Write Write Write Reg Reg Reg Reg

Write Add. Decode	1M x 18 Array	1M x 18 Array	1M x 18 Array	1M x 18 Array
	Read Data Reg.
		72	36
			36

Read Add. Decode

Reg.

Reg.

Address					20			A(19:0)
Register
	Control					RPS
		Logic
										CQ
									CQ
				18
			Reg.
				18			18
				18					Q[17:0]
				18
									QVLD

Logic Block Diagram (CY7C1545V18)

36

D[35:0]

19Address

A(18:0) Register

K

K CLK

Gen.

DOFF

	Write	Write	Write	Write
	Reg	Reg	Reg	Reg
Decode	512K x	512K x	512K x	512K x	Decode
Write Add.	36 Array	36 Array	36 Array	36 Array	Read Add.
	Read Data Reg.

Address Register

Control

Logic

19 A(18:0)

RPS

VREF
		Control
WPS
		Logic
BWS
	[3:0]

144

72

72

					CQ
		36		CQ
Reg.	Reg.
		36	36
Reg.		36		Q[35:0]
		36
				QVLD

Document Number: 001-05389 Rev. *F Page 3 of 28

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