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Cypress CY7C1568V18, CY7C1577V18, CY7C1570V18, CY7C1566V18 manual AC Test Loads and Waveforms

Models: CY7C1570V18 CY7C1577V18 CY7C1566V18 CY7C1568V18

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CY7C1566V18, CY7C1577V18

CY7C1568V18, CY7C1570V18

AC Test Loads and Waveforms

Figure 4. AC Test Loads and Waveforms

VREF = 0.75V

VREF

0.75V

OUTPUT

Z0 = 50Ω

Device

Under

Test

RQ =

250Ω

(a)

RL = 50Ω

VREF = 0.75V

VREF

0.75V

R = 50Ω

OUTPUT

ALL INPUT PULSES[21]

1.25V

Device

5 pF 0.25V

0.75V

Under

Slew Rate = 2 V/ns

Test

RQ =

250Ω

INCLUDING

JIG AND

(b)

SCOPE

Note

21.Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, VREF = 0.75V, RQ = 250Ω, VDDQ = 1.5V, input pulse levels of 0.25V to 1.25V, output loading of the specified IOL/IOH, and load capacitance shown in (a) of AC Test Loads and Waveforms.

Document Number: 001-06551 Rev. *E

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Cypress CY7C1568V18, CY7C1577V18, CY7C1570V18, CY7C1566V18 manual AC Test Loads and Waveforms

Contents

Functional Description FeaturesConfigurations Selection Guide Logic Block Diagram CY7C1566V18 Logic Block Diagram CY7C1577V18 Logic Block Diagram CY7C1568V18 Logic Block Diagram CY7C1570V18 CY7C1566V18 8M x Pin ConfigurationBall Fbga 15 x 17 x 1.4 mm Pinout CY7C1577V18 8M x CY7C1568V18 4M x CY7C1570V18 2M x Pin Name Pin Description Pin DefinitionsSynchronous Read/Write Input. When TDO for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TCK Pin for Jtag Functional Overview Echo Clocks Valid Data Indicator QvldApplication Example SRAM#1 SRAM#2 Operation Write Cycle DescriptionsComments Device Write cycle description table for CY7C1577V18 followsWrite cycle description table for CY7C1570V18 follows Into the device. D359 remains unaltered Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram State diagram for the TAP controller follows TAP Controller Block Diagram TAP Electrical Characteristics TAP AC Switching Characteristics TAP Timing and Test Conditions Instruction Codes Identification Register DefinitionsScan Register Sizes Register Name Bit Size Boundary Scan Order Bit Number Bump ID Power Up Sequence Power Up Sequence in DDR-II+ SramPower Up Waveforms DLL Constraints Maximum Ratings Electrical CharacteristicsDC Electrical Characteristics Range Ambient Thermal Resistance AC Electrical CharacteristicsCapacitance Parameter Description Test Conditions Max Unit AC Test Loads and Waveforms AC Test Loads and Waveforms High Switching CharacteristicsParameter Min Max LOW NOP Switching WaveformsRead/Write/Deselect Sequence 29, 30 Read NOP Write Ordering Information CY7C1566V18, CY7C1577V18 Package Diagram Ball Fbga 15 x 17 x 1.4 mm NXR ECN No Issue Orig. Description of Change DateDocument History IGS