Cypress CY7C1566V18, CY7C1568V18, CY7C1570V18, CY7C1577V18 - page 25

CY7C1566V18, CY7C1577V18

CY7C1568V18, CY7C1570V18

Document Number: 001-06551 Rev. *E Page 25 of 28

Ordering Information

Not all of the speed, package, and temperature ranges are available. Contact your local sales representative or

visit www.cypress.com for actual products offered.

Speed

(MHz) Ordering Code Package

Diagram Package Type Operating

Range

400 CY7C1566V18-400BZC 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Commercial

CY7C1577V18-400BZC

CY7C1568V18-400BZC

CY7C1570V18-400BZC

CY7C1566V18-400BZXC 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

CY7C1577V18-400BZXC

CY7C1568V18-400BZXC

CY7C1570V18-400BZXC

CY7C1566V18-400BZI 51-85195 165-Ball Fine Pitch Ba ll Grid Array (15 x 17 x 1.4 mm) Industrial

CY7C1577V18-400BZI

CY7C1568V18-400BZI

CY7C1570V18-400BZI

CY7C1566V18-400BZXI 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

CY7C1577V18-400BZXI

CY7C1568V18-400BZXI

CY7C1570V18-400BZXI

375 CY7C1566V18-375BZC 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Commercial

CY7C1577V18-375BZC

CY7C1568V18-375BZC

CY7C1570V18-375BZC

CY7C1566V18-375BZXC 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

CY7C1577V18-375BZXC

CY7C1568V18-375BZXC

CY7C1570V18-375BZXC

CY7C1566V18-375BZI 51-85195 165-Ball Fine Pitch Ba ll Grid Array (15 x 17 x 1.4 mm) Industrial

CY7C1577V18-375BZI

CY7C1568V18-375BZI

CY7C1570V18-375BZI

CY7C1566V18-375BZXI 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

CY7C1577V18-375BZXI

CY7C1568V18-375BZXI

CY7C1570V18-375BZXI

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Contents

Main 72-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) CY7C1566V18, CY7C1577V18 CY7C1568V18, CY7C1570V18 Features Configurations Functional Description Logic Block Diagram (CY7C1566V18) Logic Block Diagram (CY7C1577V18) 4M x 8 Array 4M x 8 Array 4M x 9 Array 4M x 9 Array Logic Block Diagram (CY7C1568V18) Logic Block Diagram (CY7C1570V18) 2M x 18 Array 2M x 18 Array 1M x 36 Array 1M x 36 Array Pin Configuration 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1566V18, CY7C1577V18 CY7C1568V18, CY7C1570V18 Pin Configuration 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1566V18, CY7C1577V18 CY7C1568V18, CY7C1570V18 Pin Definitions CY7C1566V18, CY7C1577V18 CY7C1568V18, CY7C1570V18 Pin Definitions CY7C1566V18, CY7C1577V18 CY7C1568V18, CY7C1570V18 Functional Overview Read Operations Write Operations Byte Write Operations Application Example BUS MASTER (CPU or ASIC) SRAM#1 SRAM#2 Truth Table Page IEEE 1149.1 Serial Boundary Scan (JTAG) Disabling the JTAG Feature Test Access PortTest Clock Test Mode Select (TMS) Test D ata- In (T DI) Page TAP Controller State Diagram CY7C1566V18, CY7C1577V18 CY7C1568V18, CY7C1570V18 TAP Controller Block Diagram TAP Electrical Characteristics TAP AC Switching Characteristics TAP Timing and Test Conditions Identification Register Definitions Scan Register Sizes Instruction Codes CY7C1566V18, CY7C1577V18 CY7C1568V18, CY7C1570V18 Boundary Scan Order Power Up Sequence in DDR-II+ SRAM Power Up Sequence Clock Start (Clock Starts after VDD/VDDQ is Stable) Fix HIGH (tie to VDDQ) DLL Constraints Maximum Ratings Operating Range Electrical Characteristics DC Electrical Characteristics AC Electrical Characteristics Capacitance Thermal Resistance Electrical Characteristics DC Electrical Characteristics AC Test Loads and Waveforms Figure 4. AC Test Loads and Waveforms [+] Feedback [+] Feedback ZQ ZQ RQ = 250 (b) Switching Characteristics Switching Waveforms Read/Write/Deselect Sequence READ READ 12345678910 Figure 5. Waveform for 2.5 Cycle Read Latency Page Ordering Information Package Diagram Figure 6. 165-Ball FBGA (15 x 17 x 1.4 mm) [+] Feedback [+] Feedback 51-85195-*A Document History Page