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Cypress CY7C1577V18 Switching Waveforms, Read/Write/Deselect Sequence 29, 30, Nop, Read NOP Write

Models: CY7C1570V18 CY7C1577V18 CY7C1566V18 CY7C1568V18

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CY7C1566V18, CY7C1577V18

CY7C1568V18, CY7C1570V18

Switching Waveforms

Read/Write/Deselect Sequence [29, 30, 31]

Figure 5. Waveform for 2.5 Cycle Read Latency

K

NOP

1

tKH

	READ	READ	NOP	NOP	NOP	WRITE	WRITE	READ	NOP	NOP
	2	3	4	5	6	7	8	9	10	11	12
tKL	tCYC	tKHKH

K

LD tSC tHC

R/W

A

QVLD

DQ

CQ

CQ

A0	A1			A2	A3	A4
	t						tQVLD
tSA tHA	tQVLD						tQVLD
				tHD	tSD	tHD
		Q10		tSD	tSD
	Q00 Q01	Q10		Q11	D20 D21	D30 D31	Q40
	tCLZ	tDOH		tCHZ
	tCO			tCQD
(Read Latency = 2.5 Cycles)				tCQDOH
	tCCQO			tCQDOH
	tCQOH
	tCQOH	t	CCQO		tCQH	tCQHCQH
			CCQO

DON’T CARE

UNDEFINED

Notes

29.Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0 + 1.

30.Outputs are disabled (High Z) one clock cycle after a NOP.

31.In this example, if address A4 = A3, then data Q40 = D30 and Q41 = D31. Write data is forwarded immediately as read results. This note applies to the whole diagram.

Document Number: 001-06551 Rev. *E

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Cypress CY7C1577V18, CY7C1570V18, CY7C1568V18 Switching Waveforms, Read/Write/Deselect Sequence 29, 30, Nop, Read NOP Write

Contents

Features ConfigurationsFunctional Description Selection Guide Logic Block Diagram CY7C1566V18 Logic Block Diagram CY7C1577V18 Logic Block Diagram CY7C1568V18 Logic Block Diagram CY7C1570V18 Pin Configuration Ball Fbga 15 x 17 x 1.4 mm PinoutCY7C1566V18 8M x CY7C1577V18 8M x CY7C1568V18 4M x CY7C1570V18 2M x Pin Definitions Pin Name Pin DescriptionSynchronous Read/Write Input. When Power Supply Inputs to the Core of the Device Power Supply Inputs for the Outputs of the DeviceTDO for Jtag TCK Pin for Jtag Functional Overview Valid Data Indicator Qvld Application ExampleEcho Clocks SRAM#1 SRAM#2 Write Cycle Descriptions OperationComments Write cycle description table for CY7C1577V18 follows Write cycle description table for CY7C1570V18 followsDevice Into the device. D359 remains unaltered Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram State diagram for the TAP controller follows TAP Controller Block Diagram TAP Electrical Characteristics TAP AC Switching Characteristics TAP Timing and Test Conditions Identification Register Definitions Scan Register SizesInstruction Codes Register Name Bit Size Boundary Scan Order Bit Number Bump ID Power Up Sequence in DDR-II+ Sram Power Up WaveformsPower Up Sequence DLL Constraints Electrical Characteristics DC Electrical CharacteristicsMaximum Ratings Range Ambient AC Electrical Characteristics CapacitanceThermal Resistance Parameter Description Test Conditions Max Unit AC Test Loads and Waveforms AC Test Loads and Waveforms Switching Characteristics Parameter Min MaxHigh LOW Switching Waveforms Read/Write/Deselect Sequence 29, 30NOP Read NOP Write Ordering Information CY7C1566V18, CY7C1577V18 Package Diagram Ball Fbga 15 x 17 x 1.4 mm ECN No Issue Orig. Description of Change Date Document HistoryNXR IGS