CY7C64013C
CY7C64113C
Document #: 38-08001 Rev. *B Page 21 of 51
Q1, Q2, and Q3 discussed below are the transistors referenced in Figure 9-1. The available GPIO drive strength are:
• Output LOW Mode: The pin’s Data Register is set to ‘0’
Writing ‘0’ to the pin’s Data Register puts the pin in output LOW mode, regardless of the contents of the Port Configuration
Bits[1:0]. In this mode, Q1 and Q2 are OFF. Q3 is ON. The GPIO pin is driven LOW through Q3.
•Output HIGH Mode: The pin’s Data Register is set to 1 and the Port Configuration Bits[1:0] is set to ‘10’
In this mode, Q1 and Q3 are OFF. Q2 is ON. The GPIO is pulled up through Q2. The GPIO pin is capable of sourcing... of
current.
•Resistive Mode: The pin’s Data Register is set to 1 and the Port Configuration Bits[1:0] is set to ‘11’
Q2 and Q3 are OFF. Q1 is ON. The GPIO pin is pulled up with an internal 14kΩ resistor. In resistive mode, the pin may serve
as an input. Reading the pin’s Data Register returns a logic HIGH if the pin is not driven LOW by an external source.
•Hi-Z Mode: The pin’s Data Register is set to1 and Port Configuration Bits[1:0] is set either ‘00’ or ‘01’
Q1, Q2, and Q3 are all OFF. The GPIO pin is not driven internally. In this mode, the pin may serve as an input. Reading the
Port Data Register returns the actual logic value on the port pins.

9.2 GPIO Interrupt Enable Ports

Each GPIO pin can be individually enabled or disabled as an interrupt source. The Port 0–3 Interrupt Enable registers provide
this feature with an interrupt enable bit for each GPIO pin. When HAPI mode (discussed in Section 14.0) is enabled the GPIO
interrupts are blocked, including ports not used by HAPI, so GPIO pins cannot be used as interrupt sources.
During a reset, GPIO interrupts are disabled by clearing all of the GPIO interrupt enable ports. Writing a ‘1’ to a GPIO Interrupt
Enable bit enables GPIO interrupts from the corresponding input pin. All GPIO pins share a common interrupt, as discussed in
Section 16.7
Port 0 Interrupt Enable ADDRESS 0x04
Port 2 Interrupt Enable ADDRESS 0x06
Port 3 Interrupt Enable ADDRESS 0x07
10.0 DAC Port
The CY7C64113C features a programmable current sink 4 bit port which is also known as a DAC port. Each of these port I/O
pins have a programmable current sink. Writing a ‘1’ to a DAC I/O pin disables the output current sink (Isink DAC) and drives the
I/O pin HIGH through an integrated 14-kΩ resistor. When a ‘0’ is written to a DAC I/O pin, the Isink DAC is enabled and the pull-
up resistor is disabled. This causes the Isink DAC to sink current to drive the output LOW. Figure 10-1 shows a block diagram of
the DAC port pin.
Bit # 76543210
Bit Name P0.7 Intr Enable P0.6 Intr Enable P0.5 Intr Enable P0.4 Intr Enable P0.3 Intr Enable P0.2 Intr Enable P0.1 Intr Enable P0.0 Intr Enable
Read/Write WWWWWWWW
Reset 00000000
Figure 9-7. Port 0 Interrupt Enable
Bit # 76543210
Bit Name P1.7 Intr Enable P1.6 Intr Enable P1.5 Intr Enable P1.4 Intr Enable P1.3 Intr Enabl P1.2 Intr Enable P1.1 Intr Enable P1.0 Intr Enable
Read/Write WWWWWWWW
Reset 00000000
Figure 9-8. Port 1 Interrupt Enable
Bit # 76543210
Bit Name P2.7 Intr Enable P2.6 Intr Enable P2.5 Intr Enable P2.4 Intr Enable P2.3 Intr Enable P2.2 Intr Enable P2.1 Intr Enable P2.0 Intr Enable
Read/Write WWWWWWWW
Reset 00000000
Figure 9-9. Port 2 Interrupt Enable
Bit # 76543210
Bit Name Reserved
(Set to 0)
P3.6 Intr Enable P3.5 Intr Enable P3.4 Intr Enable P3.3 Intr Enable P3.2 Intr Enable P3.1 Intr Enable P3.0 Intr Enable
Read/Write WWWWWWWW
Reset 00000000
Figure 9-10. Port 3 Interrupt Enable
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