CY7C64013C
CY7C64113C
Document #: 38-08001 Rev. *B Page 8 of 51
Logic Block Diagram
Interrupt
Controller
PROM
12-bit
Timer
Reset
Watchdog
Timer
Power-On
SCLK
I2C
GPIO
PORT 1
GPIO
PORT 0
P0[7:0]
P1[2:0]
P1[7:3]
SDATA
8-bit Bus
6-MHz crystal
RAM
USB
SIE
USB
Transceiver
D+[0]
D–[0]
Upstream
USB Port
P3[2:0]
DAC
PORT
DAC[0]
DAC[2]
High Current
Outputs
CY7C64113C only
256 byte
8 KB
Clock
6 MHz
12-MHz
8-bit
CPU
*I2C-compatible interface enabled by firmware through
Interface
P3[7:3]
Additional
Outputs
High Current
PLL
12 MHz
48 MHz
Divider
GPIO/
PORT 2
P2[0,1,7]
P2[3]; Data_Ready
P2[4]; STB
P2[5]; OE
P2[6]; CS
P2[2]; Latch_Empty
HAPI
P2[1:0] or P1[1:0]
CY7C64113C only
PORT 3
GPIO
DAC[7]
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