CY7C64013C
CY7C64113C
Document #: 38-08001 Rev. *B Page 26 of 51
Bit 7 : MSTR Mode
Setting this bit to 1 causes the I2C-compatible block to initiate a master mode transaction by sending a start bit and
transmitting the first data byte from the data register (this typically holds the target address and R/W bit). Subsequent bytes
are initiated by setting the Continue bit, as described below.
Clearing this bit (set to 0) causes the GPIO pins to operate normally
In master mode, the I2C-compatible block generates the clock (SCK), and drives the data line as required depending on
transmit or receive state. The I2C-compatible block performs any required arbitration and clock synchronization. IN the
event of a loss of arbitration, this MSTR bit is cleared, the ARB Lost bit is set, and an interrupt is generated by the
microcontroller. If the chip is the target of an external master that wins arbitration, then the interrupt is held off until the
transaction from the external master is completed.
When MSTR Mode is cleared from 1 to 0 by a firmware write, an I2C Stop bit is generated.
Bit 6 : Continue / Busy
This bit is written by the firmware to indicate that the firmware is ready for the next byte transaction to begin. In other words,
the bit has responded to an interrupt request and has completed the required update or read of the data register. During a
read this bit indicates if the hardware is busy and is locking out additional writes to the I2C Status and Control register. This
locking allows the hardware to complete certain operations that may require an extended period of time. Following an I2C
interrupt, the I2C-compatible block does not return to the Busy state until firmware sets the Continue bit. This allows the
firmware to make one control register write without the need to check the Busy bit.
Bit 5 : Xmit Mode
This bit is set by firmware to enter transmit mode and perform a data transmit in master or slave mode. Clearing this bit
sets the part in receive mode. Firmware generally determines the value of this bit from the R/W bit associated with the I2C
address packet. The Xmit Mode bit state is ignored when initially writing the MSTR Mode or the Restart bits, as these cases
always cause transmit mode for the first byte.
Bit 4 : ACK
This bit is set or cleared by firmware during receive operation to indicate if the hardware should generate an ACK signal
on the I2C-compatible bus. Writing a 1 to this bit generates an ACK (SDA LOW) on the I2C-compatible bus at the ACK bit
time. During transmits (Xmit Mode = 1), this bit should be cleared.
Bit 3 : Addr
This bit is set by the I2C-compatible block during the first byte of a slave receive transaction, after an I2C start or restart.
The Addr bit is cleared when the firmware sets the Continue bit. This bit allows the firmware to recognize when the master
has lost arbitration, and in slave mode it allows the firmware to recognize that a start or restart has occurred.
Bit 2 : ARB Lost/Restart
This bit is valid as a status bit (ARB Lost) after master mode transactions. In master mode, set this bit (along with the
Continue and MSTR Mode bits) to perform an I2C restart sequence. The I2C target address for the restart must be written
Table 13-1. I2C Status and Control Register Bit Definitions
Bit Name Description
0I
2C Enable When set to ‘1’, the I2C-compatible function is enabled. When cleared, I2C GPIO pins
operate normally.
1 Received Stop Reads 1 only in slave receive mode, when I2C Stop bit detected (unless firmware did not
ACK the last transaction).
2 ARB Lost/Restart Reads 1 to indicate master has lost arbitration. Reads 0 otherwise.
Write to 1 in master mode to perform a restart sequence (also set Continue bit).
3 Addr Reads 1 during first byte after start/restart in slave mode, or if master loses arbitration.
Reads 0 otherwise. This bit should always be written as 0.
4 ACK In receive mode, write 1 to generate ACK, 0 for no ACK.
In transmit mode, reads 1 if ACK was received, 0 if no ACK received.
5 Xmit Mode Write to 1 for transmit mode, 0 for receive mode.
6 Continue/Busy Write 1 to indicate ready for next transaction.
Reads 1 when I2C-compatible block is busy with a transaction, 0 when transaction is
complete.
7 MSTR Mode Write to 1 for master mode, 0 for slave mode. This bit is cleared if master loses arbitration.
Clearing from 1 to 0 generates Stop bit.
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