CY7C64013C
CY7C64113C
Document #: 38-08001 Rev. *B Page 42 of 51
1 1 1 0 Out !=2 UC valid updates 1 updates UC UC 1 UC 0 0 1 1 Stall yes
1 1 1 0 Out > 10 UC x UC UC UC UC UC UC UC NoChange ignore no
1 1 1 0 Out x UC invalid UC UC UC UC UC UC UC NoChange ignore no
1 1 1 0 In x UC x UC UC UC UC 1 UC UC NoChange NAK yes
Status Out/extra In
0 0 1 0 Out 2 UC valid 1 1 updates UC UC 1 1 NoChange ACK yes
0 0 1 0 Out 2 UC valid 0 1 updates UC UC 1 UC 0 0 1 1 Stall yes
0 0 1 0 Out !=2 UC valid updates 1 updates UC UC 1 UC 0 0 1 1 Stall yes
0 0 1 0 Out > 10 UC x UC UC UC UC UC UC UC NoChange ignore no
0 0 1 0 Out x UC invalid UC UC UC UC 1 UC UC NoChange ignore no
0 0 1 0 In x UC x UC UC UC UC 1 UC UC 0 0 1 1 Stall yes
OUT ENDPOINT
Properties of Incoming Packet Changes made by SIE to Internal Registers and Mode Bits
Mode Bits token count buffer dval DTOG DVAL COUNT Setup In Out ACK Mode Bits Response Intr
Normal Out/erroneous In
1 0 0 1 Out <= 10 data valid updates 1 updates UC UC UC 1 1 0 0 0 ACK yes
1 0 0 1 Out > 10 junk x updates updates updates UC UC UC UC NoChange ignore yes
1 0 0 1 Out x junk invalid updates 0 updates UC UC UC UC NoChange ignore yes
1 0 0 1 In x UC x UC UC UC UC UC UC UC NoChange ignore no
(STALL[3] = 0)
1 0 0 1 In x UC x UC UC UC UC UC UC UC NoChange Stall no
(STALL[3] = 1)
NAK Out/erroneous In
1 0 0 0 Out <= 10 UC valid UC UC UC UC UC 1 UC NoChange NAK yes
1 0 0 0 Out > 10 UC x UC UC UC UC UC UC UC NoChange ignore no
1 0 0 0 Out x UC invalid UC UC UC UC UC UC UC NoChange ignore no
1 0 0 0 In x UC x UC UC UC UC UC UC UC NoChange ignore no
Isochronous endpoint (Out)
0 1 0 1 Out x updates updates updates updates updates UC UC 1 1 NoChange RX yes
0 1 0 1 In x UC x UC UC UC UC UC UC UC NoChange ignore no
IN ENDPOINT
Properties of Incoming Packet Changes made by SIE to Internal Registers and Mode Bits
Mode Bits token count buffer dval DTOG DVAL COUNT Setup In Out ACK Mode Bits Response Intr
Normal In/erroneous Out
1 1 0 1 Out x UC x UC UC UC UC UC UC UC NoChange ignore no
(STALL[3] = 0)
1 1 0 1 Out x UC x UC UC UC UC UC UC UC NoChange stall no
(STALL[3] = 1)
1 1 0 1 In x UC x UC UC UC UC 1 UC 1 1 1 0 0 ACK (back) yes
NAK In/erroneous Out
1 1 0 0 Out x UC x UC UC UC UC UC UC UC NoChange ignore no
1 1 0 0 In x UC x UC UC UC UC 1 UC UC NoChange NAK yes
Isochronous endpoint (In)
0 1 1 1 Out x UC x UC UC UC UC UC UC UC NoChange ignore no
0 1 1 1 In x UC x UC UC UC UC 1 UC UC NoChange TX yes
Note:
3. STALL bit is bit 7 of the USB Non-Control Device Endpoint Mode registers. For more information, refer to Sec.
Table 19-2. Details of Modes for Differing Traffic Conditions (see Table 19-1 for the decode legend) (continued)[+] Feedback